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K7D323674A Datasheet(PDF) 5 Page - Samsung semiconductor |
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K7D323674A Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 19 page Rev 1.4 1Mx36 & 2Mx18 SRAM - 5 - Oct. 2005 K7D321874A K7D323674A FUNCTIONAL BLOCK DIAGRAM K,K B1 B3 B2 Register CE Memory Array 1Mx36 Data Out Data In Advance Control SD/DD Co Clock Synchronous Buffer Internal Clock Generator CE R/W LD Data Output Strobe Data Output Enable State Machine Strobe_out S/A Array 2 : 1 MUX Data In Register Write Buffer W/D Array Echo Clock Output 36(or 18)x2 36(or 18)x2 36(or18)x2 36(or18)x2 XDIN CQ,CQ DQ 36(or 18) Select & R/W control Output Buffer Write CE Burst Counter Register Address Address Comparator 2:1 MUX Dec. 20(or 21) 18(or 19) 18(or 19) 20(or 21) (Burst Write SA[0:20]( or SA[0:21]) or (2Mx18) (2 stage) (2 stage) (Burst Address) Address) PIN DESCRIPTION Pin Name Pin Description Pin Name Pin Description K, K Differential Clocks TCK JTAG Test Clock SA Synchronous Address Input TMS JTAG Test Mode Select SA0, SA1 Synchronous Burst Address Input (SA0 = LSB) TDI JTAG Test Data Input DQ Synchronous Data I/O TDO JTAG Test Data Output CQ, CQ Differential Output Echo Clocks VREF HSTL Input Reference Voltage B1 Load External Address VDD Power Supply B2 Burst R/W Enable VDDQ Output Power Supply B3 Single/Double Data Selection VSS GND LBO Linear Burst Order NC No Connection ZQ Output Driver Impedance Control Input |
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