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M76DW52003TA Datasheet(PDF) 6 Page - STMicroelectronics |
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M76DW52003TA Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 27 page  M76DW52003TA, M76DW52003BA 6/27 SIGNAL DESCRIPTION See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A17). Addresses A0-A17 are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they con- trol the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable (EF) and Write Enable (W) signals, while the SRAM is accessed through two Chip Enable signals (E1S and E2S) and the Write Enable signal (W). Address Inputs (A18-A20). Addresses A18-A20 are inputs for the Flash component only. The Flash memory is accessed through the Chip En- able (EF) and Write Enable (W) signals Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A– 1). When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the ad- dressed Word, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to in- clude this pin when BYTE is Low except when stated explicitly otherwise. Flash Chip Enable (EF). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip En- able is at VILand RPF is at VIH the device is in ac- tive mode. When Chip Enable is at VIH the memory is deselected, the outputs are high imped- ance and the power consumption is reduced to the stand-by level. Output Enable (G). The Output Enable, G, con- trols the Bus Read operation of the device. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the device. VPP/Write Protect (VPP/WP). The VPP/Write Protect pin provides two functions. The VPP func- tion allows the Flash memory to use an external high voltage power supply to reduce the time re- quired for Program operations. This is achieved by bypassing the unlock cycles and/or using the Double Word or Quadruple Byte Program com- mands. The Write Protect function provides a hardware method of protecting the two outermost boot blocks in the Flash memory. When VPP/Write Protect is Low, VIL, the memory protects the two outermost boot blocks; Program and Erase operations in these blocks are ignored while VPP/Write Protect is Low, even when RPF is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the two outermost boot blocks. Program and Erase oper- ations can now modify the data in these blocks un- less the blocks are protected using Block Protection. When VPP/Write Protect is raised to VPP the mem- ory automatically enters the Unlock Bypass mode. When VPP/Write Protect returns to VIH or VIL nor- mal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the M29DW323D datasheet for more details. Reset/Block Temporary Unprotect (RPF). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if VPP/WP is at VIL, then the two outer- most boot blocks will remain protected even if RPF is at VID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the M29DW323D datasheet for more details. Holding RPF at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the Flash memory is performing a Program or Erase operation. During Program or Erase op- erations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. |
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