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M68AW256DL55ND1T Datasheet(PDF) 3 Page - STMicroelectronics |
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M68AW256DL55ND1T Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 20 page 3/20 M68AW256DL SUMMARY DESCRIPTION The M68AW256DL is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 262,144 words by 16 bits. The device features fully static operation re- quiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an au- tomatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW256DL is available in TFBGA48 (0.75 mm pitch) and in TSOP44 Type II packages. Figure 2. Logic Diagram Table 1. Signal Names AI05492 18 A0-A17 W DQ0-DQ15 VCC M68AW256DL G 16 E1 UB LB VSS E2 A0-A17 Address Inputs DQ0-DQ15 Data Input/Out put E1, E2 Chip Enables G Output Enable W Write Enable UB Upper Byte Enable Input LB Lower Byte Enable Input VCC Supply Voltage VSS Ground NC Not Connected Internally DU Don’t Use as Internally Connected |
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