2Mx36 & 4Mx18 DDR II SIO b2 SRAM

K7J643682M

K7J641882M

- 7 -

Rev 1.0

Aug. 2005

Single Clock Mode

K7J643682M and K7J641882M can be operated with the single clock pair K and K, insted of C or C for output clocks.

To operate these devices in single clock mode, C and C must be tied high during power up

and must be maintained high during operation.

After power up, this device can

′t change to or from single clock mode.

System flight time and clock skew could not be compensated in this mode.

Depth Expansion

Separate input and output ports enables easy depth expansion.

Each port can be selected and deselected independently and read and write operation do not affect each other.

Before chip deselected, all read and write pending operations are completed.

Clock Consideration

K7J643682M and K7J641882M utlizes internal DLL(Delay-Locked Loops) for maximum output data valid window.

It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.

Circuitry automatically resets the DLL when absence of input clock is detected.

Power-Up/Power-Down Supply Voltage Sequencing

Echo clock operation

To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,

which are synchronized with internal data output.

Echo clocks run free during normal operation.

The Echo clock is triggered by internal output clock signal, and transfered to external through same structures as output driver.

Programmable Impedance Output Buffer Operation

The value of RQ (within 15%) is five times the output impedance desired.

For example, 250

Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.

In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous

behavior in the SRAM.

There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the

SRAM needs 1024 non-read cycles.