6.42

IDT70V7288S/L

64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects

Industrial and Commercial Temperature Ranges

4

NOTES:

1.

Chip Enable references are shown above with the actual

2.

Port "A" and "B" references are located where

CE is used.

3.

4.

CE and MBSEL cannot be active at the same time.

Truth Table II – Non-Contention Read/Write Control

NOTES:

2. Refer to Truth Table I.

3.

CE and MBSEL cannot both be active at the same time.

NOTES:

2. Refer to Truth Table I.

3. Each mailbox location contains a 16-bit word, controllable in bytes by setting input levels to UB and LB appropriately.

CE

Mode

L

Port Selected (TTL Active)

< 0.2V

Port Selected (CMOS Active)

H

X

Port Deselected (TTL Inactive)

Port Deselected (TTL Inactive)

X

Port Deselected (CMOS Inactive)

X<0.2V

Port Deselected (CMOS Inactive)

4077 tbl 02

Inputs

(1)

Outputs

Mode

R/

W

OE

UB

LB

MBSEL

H

X

X

X

X

H

High-Z

High-Z

Deselected: Power-Down

X

(3)

XX

H

H

X

(3)

High-Z

High-Z

Both Bytes Deselected

LL

X

L

H

H

High-Z

Write to Upper Byte Only

L

L

X

H

L

H

High-Z

Write to Lower Byte Only

LL

X

L

L

H

Write to Both Bytes

LH

L

L

H

H

High-Z

Read Upper Byte Only

LH

LH

LH

High-Z

Read Lower Byte Only

LH

L

L

LH

Read Both Bytes

X

(3)

XH

X

X

X

(3)

High-Z

High-Z

Outputs Disabled

4077 tbl 03

Inputs

Outputs

Mode

R/

W

OE

UB

LB

MBSEL

HH

L

Read Data from Mailbox,

↓ clears interrupt

H

H

LLL

L

Read Data from Mailbox,

↓ clears interrupt

HL

X

Write Data into Mailbox

L

XXXX

L

____

____

Not Allowed

4077 tbl 04