6.42

IDT70V7288S/L

64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects

Industrial and Commercial Temperature Ranges

2

Description

The IDT70V7288 is a high-speed 64K x 16 (1M bit) Bank-Switch-

able Dual-Ported SRAM organized into four independent 16K x 16

banks. The device has two independent ports with separate controls,

addresses, and I/O pins for each port, allowing each port to asynchro-

nously access any 16K x 16 memory block not already accessed by the

other port. Accesses by the ports into specific banks are controlled via

bank select pin inputs under the user's control. Mailboxes are provided

to allow inter-processor communications. Interrupts are provided to

indicate mailbox writes have occurred. An automatic power down

feature controlled by the chip enables (

chip circuitry of each port to enter a very low standby power mode and

allows fast depth expansion.

The IDT70V7288 offers a maximum address-to-data access time

as fast as 15ns, and is packaged in a 100-pin Thin Quad Flatpack

(TQFP).

Functionality

The IDT70V7288 is a high-speed asynchronous 64K x 16 Bank-

Switchable Dual-Ported SRAM, organized in four 16K x 16 banks. The

two ports are permitted independent, simultaneous access into sepa-

rate banks within the shared array. There are four user-controlled

Bank Select input pins, and each of these pins is associated with a

specific bank within the memory array. Access to a specific bank is

gained by placing the associated Bank Select pin in the appropriate

the right port (See Truth Table IV). Once a bank is assigned to a

particular port, the port has full access to read and write within that

bank. Each port can be assigned as many banks within the array as

needed, up to and including all four banks.

The IDT70V7288 provides mailboxes to allow inter-processor

communications. Each port has four 16-bit mailbox registers available

to which it can write and read and which the opposite port can read

only. These mailboxes are external to the common SRAM array, and

are accessed by setting

mailbox has an associated interrupt: a port can generate an interrupt

to the opposite port by writing to the upper byte of any one of its four

16-bit mailboxes. The interrupted port can clear the interrupt by

reading the upper byte. This read will not alter the contents of the

mailbox.

If desired, any source of interrupt can be independently masked via

software. Two registers are provided to permit interpretation of inter-

rupts: the Interrupt Cause Register and the Interrupt Status Register.

The Interrupt Cause Register gives the user a snapshot of what has

caused the interrupt to be generated - the specific mailbox written to.

The information in this register provides post-mask signals: Interrupt

sources that have been masked will not be updated. The Interrupt

Status Register gives the user the status of all bits that could potentially

cause an interrupt regardless of whether they have been masked.

Truth Table V gives a detailed explanation of the use of these registers.