6.42

IDT70V7288S/L

64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects

Industrial and Commercial Temperature Ranges

7

AC Test Conditions

Figure 1. AC Output Test Load

Figure 2. Output Test Load

*Including scope and jig.

Figure 3. Lumped Capacitance Load Typical Derating Curve

AC Electrical Characteristics Over the

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2.

This parameter is guaranteed by device characterization, but is not production tested.

3.

To access RAM,

4.

'X' in part numbers indicates power rating (S or L).

5.

Refer to Truth Table I.

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns Max.

1.5V

1.5V

Figures 1,2 and 3

4077 tbl 11

4077 drw 03

590

Ω

30pF

435

Ω

3.3V

INT

590

Ω

5pF*

435

Ω

3.3V

4077 drw 04

(Typical, ns)

4077 drw 05

1

2

3

4

5

6

7

8

20 40

100

60 80

120 140 160 180 200

Capacitance (pF)

-1

0

- 10pF is the I/O capacitance

of this device, and 30pF is the

AC Test Load Capacitance

,

70V7288X15

Com'l Only

70V7288X20

Com'l Only

70V7288X25

Com'l & Ind

Unit

Symbol

Parameter

Min.Max.Min.Max.Min.Max.

READ CYCLE

Read Cycle Time

15

____

20

____

25

____

ns

Address Access Time

____

15

____

20

____

25

ns

Chip Enable Access Time

(3)

____

15

____

20

____

25

ns

____

15

____

20

____

25

ns

Output Enable Access Time

____

9

____

10

____

11

ns

Output Hold from Address Change

3

____

3

____

3

____

ns

Output Low-Z Time

(1,2)

0

____

0

____

0

____

ns

____

8

____

9

____

10

ns

Chip Enab le to Power Up Time

(2,5)

0

____

0

____

0

____

ns

Chip Disable to Power Down Time

(2,5)

____

15

____

20

____

25

ns

Mailbox Flag Update Pulse (

OE or MBSEL)10

____

10

____

10

____

ns

Mailbox Address Access Time

____

15

____

20

____

25

ns

4077 tbl 12