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INDUSTRIALTEMPERATURERANGE

IDT5V994

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

AUGUST 2002

2002

Integrated Device Technology, Inc.

DSC 5828/4

c

INDUSTRIAL TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Ref input is 5V tolerant

• 4 pairs of programmable skew outputs

• Low skew: 200ps same pair, 250ps all outputs

• Selectable positive or negative edge synchronization:

Excellent for DSP applications

• Synchronous output enable

• Input frequency: 17.5MHz to 133MHz

• Output frequency: 17.5MHz to 133MHz

• 2x, 4x, 1/2, and 1/4 outputs (of VCO frequency)

• 3-level inputs for skew control

• PLL bypass for DC testing

• External feedback, internal loop filter

• 12mA balanced drive outputs

• Low Jitter: <200ps cycle-to-cycle

• Available in PLCC and TQFP packages

FUNCTIONAL BLOCK DIAGRAM

sO E

Skew

Select

1F1:0

3

3

Skew

Select

2F1:0

3

REF

PLL

FB

3

Skew

Select

3F1:0

3

3

Skew

Select

4F1:0

3

3

PE TEST

IDT5V994

3.3V PROGRAMMABLE

SKEW PLL CLOCK DRIVER

TURBOCLOCK™ PLUS

DESCRIPTION

The IDT5V994 is a high fanout 3.3V PLL based clock driver intended for

high performance computing and data-communications applications. A key

feature of the programmable skew is the ability of outputs to lead or lag the

REF input signal. The IDT5V994 has eight programmable skew outputs in

four banks of 2. Skew is controlled by 3-level input signals that may be hard-

wired to appropriate HIGH-MID-LOW levels.

When thesOE pin is held low, all the outputs are synchronously enabled.

However, if sOE is held high, all the outputs except 3Q0 and 3Q1 are

synchronously disabled.

Furthermore, when the PE is held high, all the outputs are synchronized

with the positive edge of the REF clock input. When PE is held low, all the

outputs are synchronized with the negative edge of REF. The IDT5V994

has LVTTL outputs with 12mA balanced drive outputs.