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LM5106SD Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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LM5106SD Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 12 page Connection Diagram 20175901 10-Lead MSOP or LLP See NS Number MUB10A, SDC10A Ordering Information Ordering Number Package Type NSC Package Drawing Supplied As LM5106MM MSOP-10 MUB10A 1000 shipped as Tape & Reel LM5106MMX MSOP-10 MUB10A 3500 shipped as Tape & Reel LM5106SD LLP-10 SDC10A 1000 shipped as Tape & Reel LM5106SDX LLP-10 SDC10A 4500 shipped as Tape & Reel Pin Descriptions Pin Name Description Application Information 1 VDD Positive gate drive supply Decouple VDD to VSS using a low ESR/ESL capacitor, placed as close to the IC as possible. 2 HB High side gate driver bootstrap rail Connect the positive terminal of bootstrap capacitor to the HB pin and connect negative terminal to HS. The Bootstrap capacitor should be placed as close to IC as possible. 3 HO High side gate driver output Connect to the gate of high side N-MOS device through a short, low inductance path. 4 HS High side MOSFET source connection Connect to the negative terminal of the bootststrap capacitor and to the source of the high side N-MOS device. 5 NC Not Connected 6 RDT Dead-time programming pin A resistor from RDT to VSS programs the turn-on delay of both the high and low side MOSFETs. The resistor should be placed close to the IC to minimize noise coupling from adjacent PC board traces. 7 EN Logic input for driver Disable/Enable TTL compatible threshold with hysteresis. LO and HO are held in the low state when EN is low. 8 IN Logic input for gate driver TTL compatible threshold with hysteresis. The high side MOSFET is turned on and the low side MOSFET turned off when IN is high. 9 VSS Ground return All signals are referenced to this ground. 10 LO Low side gate driver output Connect to the gate of the low side N-MOS device with a short, low inductance path. NA EP Exposed Pad The exposed pad has no electrical contact. Connect to system ground plane for reduced thermal resistance. www.national.com 2 |
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