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AS4LC2M8S0-7TC Datasheet(PDF) 4 Page - Alliance Semiconductor Corporation |
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AS4LC2M8S0-7TC Datasheet(HTML) 4 Page - Alliance Semiconductor Corporation |
4 / 29 page ® 5/21/01; v.1.1 Alliance Semiconductor P. 4 of 29 AS4LC2M8S1 AS4LC1M16S1 Operating modes 1 OP= operation code. A0~A11 see page 5. 2 MRS can be issued only when both banks are precharged and no data burst is ongoing. A new command can be issued 2 clock cycles after MRS. 3 Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic. Auto/self refresh can only be issued after both banks are precharged. 4 A11: bank select address. If low during read, write, row active and precharge, bank A is selected. If high during those states, bank B is selected. Both banks are selected and A11 is ignored if A10 is high during row precharge. 5 A new read/write/deac command to the same bank cannot be issued during a burst read/write with auto precharge. A new row active command can be issued after tRP from the end of the burst. 6 Burst stop command valid at every burst length except full-page burst. 7 DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0). Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2). Command CKEn-1 CKEn CS RAS CAS WE DQM A11 A10 A9–A0 Note Mode register set H X L L L L X Op code 1,2 Auto refresh H H LLL H X X 3 Self refresh Entry H LLLL H X X 3 Exit L H LH H H X X 3 H X XXX X 3 Bank activate H X L L H H X V* * V = Valid. row address Read Auto precharge disable HX L H L H X V L column address 4 Auto precharge enable H 4,5 Write Auto precharge disable HX L H L L X V L column address 4 Auto precharge enable H 4,5 Burst stop H X L H H L X X 6 Precharge Selected bank HX L L H L X VL X Both banks X H Clock suspend or active power down Entry H L H X XXX X L V VVX Exit L H XX XXX Precharge power down mode Entry H L H X XXX X LH H H X Exit L H H X XXX LH H H X DQM H XXX XXVX X X 7 No operation command H X H X XXX X LH H H X |
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