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AS4LC4M4F1-50TI Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
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AS4LC4M4F1-50TI Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
2 / 14 page AS4LC4M4F1 5/16/01; v.1.0 Restored Alliance Semiconductor P. 2 of 14 ® Functional description The AS4LC4M4F1 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) device organized as 4,194,304 words × 4 bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in PC, workstation, router and switch applications. This device features a high speed page-mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to CAS assertion. Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using: •RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence. • Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with previous valid data. •CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally. Outputs are high-impedence (OE and WE are don't care). • Normal read or write cycles refresh the row being accessed. • Self-refresh cycles The AS4LC4M4F1 is available in the standard 24/26-pin plastic SOJ. TSOP 24/26-pin availability is to be determined. The AS4LC4M4F1 operates with a single power supply of 3.3V ± 0.3V and provides TTL compatible inputs and outputs. Logic block diagram for 2K refresh Recommended operating conditions †V IL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified. Parameter Symbol Min Nominal Max Unit Supply voltage VCC 3.0 3.3 3.6 V GND 0.0 0.0 0.0 V Input voltage VIH 2.0 – VCC+0.5V V VIL –0.5† –0.8 V Ambient operating temperature Commercial TA 0– 70 °C Industrial -40 – 85 RAS clock generator 2048 × 2048 × 4 Array (16,777,216) Sense amp A0 A1 A2 A3 A4 A5 A6 A7 VCC GND A8 Column decoder Substrate bias generator Data I/O buffers OE RAS CAS WE clock generator WE I/O0 to I/O3 CAS clock generator A9 A10 |
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