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SP8505KS Datasheet(PDF) 9 Page - Sipex Corporation

Part # SP8505KS
Description  12-Bit Sampling A/D Converters
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Manufacturer  SIPEX [Sipex Corporation]
Direct Link  http://www.sipex.com
Logo SIPEX - Sipex Corporation

SP8505KS Datasheet(HTML) 9 Page - Sipex Corporation

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51
R/C
BUSY
Converter
Mode
Data
BUS
Acquire
Convert
Acquire
Convert
Data Valid
Hi-Z State
Hi-Z State
Data Valid
t
W
tDBC
t
B
tDBE
tA
tC
tAP
tHDR and tHL
tDB
Figure 5. Convert Mode Timing — R/C Pulse LOW, Outputs Enabled After Conversion
Series may draw excessive current. In normal
operation, this is not a problem because both pins
will be soldered together. However, during evalu-
ation, incoming inspection, repair, etc., where the
potential of a “Hot Socket” exists, care should be
taken to apply power to the SP85XX Series only
after it has been socketed.
Minimizing “Glitches”
Coupling of external transients into an analog-to-
digitalconvertercancauseerrorswhicharedifficultto
debug. In addition to the discussions earlier on layout
considerationsforsupplies,bypassingandgrounding,
there are several other useful steps that can be taken to
get the best analog performance out of a system using
the SP85XX Series. These potential system problem
sources are particularly important to consider when
developing a new system, and looking for the causes
of errors in breadboards.
First, care should be taken to avoid glitches during
critical times in the sampling and conversion process.
SincetheSP85XXSerieshasaninternalsample/hold
function, the signal that puts it into the hold state (R/C
going LOW) is critical, as it would be on any sample/
hold amplifier. The R/C falling edge should have a 5
to 10ns transition time, low jitter, and have minimal
ringing, especially during the 20ns after it falls.
R/C
BUSY
Converter
Mode
Data
BUS
Acquire
Convert
Acquire
Convert
Data
Valid
Hi-Z State
Hi-Z State
t
W
tDBC
t
B
tDBE
tA
tC
tAP
tHDR and tHL
tAP
Data
Valid
Hi-Z State
tDD
Figure 6. Read Mode Timing — R/C Pulse HIGH, Outputs Enabled Only When R/C is High


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