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SP9502KS Datasheet(PDF) 6 Page - Sipex Corporation

Part # SP9502KS
Description  Dual, 12-Bit, Voltage Output D/A Converter
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Manufacturer  SIPEX [Sipex Corporation]
Direct Link  http://www.sipex.com
Logo SIPEX - Sipex Corporation

SP9502KS Datasheet(HTML) 6 Page - Sipex Corporation

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SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
© Copyright 1999 Sipex Corporation
6
USING THE SP9502 WITH
DOUBLE-BUFFERED INPUTS
Loading Data
To load a 12-bit word to the input register of each
DAC, using a 12-bit data bus, the sequence is as
follows:
1) Set XFER=1, B1/B2=1, CLR=1, WR1=1,
WR2=1, CS=1.
2) Set A (the DAC address) to the desired
DAC — 0 = DAC
1; 1 = DAC2.
3) Set D11 (MSB) through D0 (LSB) to the
desired digital input code.
4) Load the word to the selected DAC by
cycling WR1 and CS through the following
sequence:
“1” — “0” — “1”
5) Repeat sequence for each input register.
To load a 12-bit word to the input register of each
DAC, using an 8-bit data bus, the sequence is as
follows:
1) Set XFER=1, B1/B2=1, CLR=1, WR1=1,
WR2=1, CS=1.
2) Set D11 through D4 to the 8 MSB’s of the
desired digital input code.
3) Load the 8 MSB’s of the digital word to the
selected input register by cycling WR1 and
CS through the “1” — “0” — “1” sequence.
4) Reset B1/B2 from “1” —— “0”.
5) Set D11 (MSB) through D8 to the 4 LSB’s
of the digital input code.
6) Load the 4 LSB’s by cycling WR1 and CS
through the “1” — “0” — “1” sequence.
7) Repeat sequence for each input register
TRANSFERRING DATA
To transfer the 12-bit words in the two input
registers to the two DAC registers:
1) Set CLR=1, CS=1, WR1=1.
DAC
3 TO 7
DECODE
&
5 BITS
8–BIT
LATCH
4-BIT
LATCH
DB11-DB8
DB7-DB4
Ref In
+
VOUT
44
44
4
MUX
4
4
4
8
12
DB3-DB0
INPUT
REGISTER
DAC
REGISTER
LATCH
40K 40K
Figure 1. Detailed Block Diagram (only one DAC shown)
2) Cycle WR2 and XFER through the “1” —
“0” — “1” sequence.
TosettheoutputsofthetwoDAC’sto0V,cycleWR2
and CLR through the “1” — “0” — “1” sequence,
while keeping XFER=1.
ONE LATCH, OR NO LATCHES
The latches that form the registers can be used in a
“semi-” transparent mode, and a “fully-” transparent
mode. In order to use the SP9502 in either mode the
user must be interfaced to a 12-bit bus only (B1=1).
Thesemi–transparentmodeissetupsuchthatthefirst
set of latches is transparent and the second set is used
to latch the incoming data. Data is latched into the
secondsetratherthanthefirstset,inordertominimize
glitchenergyinducedfromthedataformatting. Inthis
mode,WR1andCSaretiedlow,andWR2andXFER
areusedtostrobethedatatotheaddressedDAC. Each
DAC is addressed using the address line A. After the
appropriate DAC has been selected and the data is
settled at the digital inputs, bringing WR2 and XFER
low will transfer the data to the addressed DAC. The
user should be sure to bring XFER and WR2 high
again so that the next selected DAC will not be
overwritten by the last digital code. This mode of
operation may be useful in applications where
preloading of the input registers is not necessary;
Figure 3, top.
A fully transparent mode is realized by tying WR1,
CS, WR2, and XFER all low. In this mode, anything
that is written on the 12-bit data bus will be passed
directly to the selected DAC. Since both latches are
not being used, the previous digital word will be
overwritten by the new data as soon as the address
changes.This may be useful should the user want
to calibrate a circuit, by taking full scale or zero
scale readings for both DAC’s; Figure 3, bottom.


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