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SP9840KN Datasheet(PDF) 3 Page - Sipex Corporation

Part # SP9840KN
Description  8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC
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Manufacturer  SIPEX [Sipex Corporation]
Direct Link  http://www.sipex.com
Logo SIPEX - Sipex Corporation

SP9840KN Datasheet(HTML) 3 Page - Sipex Corporation

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259
SPECIFICATIONS (continued)
V
DD = +5V, All VINX= +0V, VREFL = 1.625, TA = 25° C for commercial–grade parts;
T
MIN ≤ TA =
T
MAX for industrial–grade parts; specifications apply to all
DAC's unless noted otherwise.)
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
DAC OUTPUTS
Voltage Range
0
V
DD – 1.5
V
R
L = 5kΩ, VDD = 4.75V
Output Current
±10
±15
mA
Note 7
Capacitive Load
47,000
pF
No Oscillation
DIGITAL OUTPUT
Logic High
3.5
V
I
OH = –0.4mA
Logic Low
0.4
V
I
OL = 1.5mA
POWER REQUIREMENTS
Power Supply Range
4.75
5.00
5.25
V
To rated specifications
Positive Supply Current
14
mA
PR = LOW
Power Dissipation
70
mW
PR = LOW
ENVIRONMENTAL AND MECHANICAL
Operating Temperature Range
Commercial
0
+70
°C
Industrial
–40
+85
°C
Storage Temperature Range
–65
+150
°C
Package
SP9840N
24–pin, 0.3" Plastic DIP
SP9840S
24–pin 0.3" SOIC
SP9843S
20–pin, 0.3" SOIC
Note 8
Notes:
1.
Code dependent
2.
All V
IN(x) = GND; D = 55H
3.
Offset binary refers to the output voltage with respect to the signal ground at V
REFL. For a positive
V
IN(x), the output will increase from negative fullscale to VREFL to positive (fullscale–1 LSB) as the
input code is incremented from 0 to 128 to 255. Note that when V
IN(x) is tied to ground and VREFL is
driven to +1.625V, as in the production tests above, then the resulting DC at V
OUT(x) will decrease
from +2V
REFL to VREFL/128 as the code is increased from 00H to FFH, due to the VIN(x) input being tied
negative with respect to V
REFL.
4.
The op amp limits linearity for V
OUT <100mV. When VIN(x) is driven above ground such that the
output voltage remains above 100mV, then the linearity specifications apply to all codes. For
V
REFL=1.625V, and VIN(x)=GND, codes 248 through 255 are not included in differential or integral
linearity tests. Integral and differential linearity are computed with respect to the best fit straight line
through codes 0 through 248.
5.
SP9840 is measured between adjacent channels, F=100kHz. SP9843 is measured between
adjacent pairs, F=100kHz.
6.
SP9843 only; measured between channels with shared input; D = 7F
H to 80H
7.
∆V
OUT < 10mV, VREFL
= 1.625V, PR = LOW.
8.
For plastic DIP, consult factory


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