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SP9840KN Datasheet(PDF) 5 Page - Sipex Corporation |
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SP9840KN Datasheet(HTML) 5 Page - Sipex Corporation |
5 / 10 page 261 Pin 9 — V OUTF — DACF Voltage Output. Pin 10 — V OUTG — DACG Voltage Output. Pin 11 — V OUTH — DACH Voltage Output. Pin12—V ING/H — DACG and H Reference Voltage Input. Pin 13 — LOADH — Load DAC Register Strobe; active high input that transfers the data bits from the Serial Input Register into the decoded DAC Register. Refer to Table 1. Pin14—CLOCK—SerialClockInput;positive-edge triggered. Pin15—SDO—SerialDataOutput;activetotem-pole output. Pin 16 — GND — Ground. Pin 17 — SDI — Serial Data Input. Pin 18 — V DD — Positive 5V Power Supply. Pin19—V INC/D — DACC and D Reference Voltage Input. Pin 20 — V OUTD — DACD Voltage Output. SP9840/SP9843 Theory of Operation Each of the eight channels of the SP9840/9843 can be used for signal reconstruction, as a pro- grammable DC source, or as a programmable signed attenuator of –1 to +0.992 times a multi- plying AC reference input. The rugged wideband output amplifiers provide both current sink and source capability to DC applications, even into difficult loads. The DC source mode mimics the functionality of a programmable trimpot, with the added benefit of a low–impedance buffered output. The amplifier's bandwidth and high open loop gain allow use in programmable signed attenuator applications where even low–distor- tion, high resolution signals, such as audio, must be gated on and off, programmable phase shifted by 0 ° or 180° or gain controlled over a –42 to 0dB range at either phase. Each channel consists of a voltage–output DAC, realized using CMOS switches and thin–film resistors in an inverted R–2R configuration. Each DAC drives the positive terminal of an op amp, configured for a gain of –1 to +1 using equal value thin–film feedback and gain–setting resistors. Signal return is the V REFL pin, the common reference input return for the eight DAC–op amp channels. As shown in Figure 1, the DAC section can be thought of as a potentiometer across V IN(X) to V REFL. If this potentiometer is set to its minimum value of 0/256, the potentiometer will have no effect on the gain, and the output will be –R F/RIN = –1 times the input. If the potentiometer could be set to 256/256, then the amplifier positive terminal would see 100% of any input and no current would flow through R IN. The circuit would behave as a non–inverting unity gain circuit, although with a noise gain of two, not one. In reality, the "potentiometer" can only be set to 255/256, and the maximum positive gain is 0.992 times the voltage between V IN(X) and V REFL. The true relation between the DC levels at the V IN(X) pins, VREFL and the output can be de- scribed as: F1 where D is programmable from 0 to 255. For single supply operation V REFL is usually externally driven to some voltage above ground — typically 1.5 to 2.5V. IF V REFL is driven to 1.5V, and V IN(X) is grounded, then code 0 would output +3.0V, and code 255 would output +11.7mV. If V REFL were grounded and VIN(X) driven to 1.5V, then codes between 0 and 128 would attempt to drive the output below ground, which will saturate the output amplifier at some voltage slightly above ground. V D VV V OUT IN REFL REFL = ()− ()∗− () + 128 1 USING THE SP9840/9843 Multiplication of Input Voltages While both the SP9840 and SP9843 are capable of four–quadrant multiplication, this terminology is not |
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