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SP9602KS Datasheet(PDF) 7 Page - Sipex Corporation

Part # SP9602KS
Description  Dual, 12-Bit, Low Power Voltage Output D/A Converter
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Manufacturer  SIPEX [Sipex Corporation]
Direct Link  http://www.sipex.com
Logo SIPEX - Sipex Corporation

SP9602KS Datasheet(HTML) 7 Page - Sipex Corporation

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SP9602DS/02
SP9602 Dual, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 1999 Sipex Corporation
7
Figure 2. Transfer Function
calibrate a circuit, by taking full scale or zero scale
readings for both DAC’s; Figure 3, bottom.
Zeroing DAC Outputs
While keeping XFER pin high, the DAC outputs can
be set to zero volts two different ways. The first
involvestheCLRandWR2pins. Innormaloperation,
the CLR pin is tied high, thus, disabling the clear
function. By cycling WR2 and CLR through "1"—
"0"—"1" sequence, a digital code of 1000 0000 0000
iswrittentobothDACregisters,producingahalfscale
output or zero volts. The second utilizes the built in
power-on-reset. Using this feature, the SP9602 can
be configured such that during power-up, the second
register will be digitally “zeroed”, producing a zero
volt output at each of the DAC outputs. This is
achievedbypoweringtheunitupwithXFERinahigh
state. Thus,withnoexternalcircuitry,theSP9602can
be powered up with the analog outputs at a known,
zero volt output level.
Temporarily Forcing
Both DAC Outputs to OV
Set WRI=1, CS=1, WR2=0, XFER=0. The DAC
registerscanbetemporarilyforcedto100000000000
bybringingtheCLRpinlow.ThiswillcausetheDAC
outputs to 0V, while the CLR pin remains low. When
the CLR pin is brought back high, the digital code at
the DAC registers will again appear at the DAC's
digital inputs, and the analog outputs will return to
their previous values.
VIn
+
VOut
D
VOut =
–1 x VIn
D
2048
(
)
VDAC =x VIn
D
4,096
VDAC
A
CS
WR1
B1/B2
WR2
XFER
CLR
FUNCTION
0
1
1
X
X
Address DAC 1 and load input register
0
0
1
X
X
Address DAC 1 and load 4 LSBs
1
1
1
X
X
Address DAC 2 and load input register
1
0
1
X
X
Address DAC 2 and load 4 LSBs
X
**
**
X
1
Transfer data from input registers to DAC registers
X
1
1
X
0
0
Temporarily force both DAC output voltages to
OV, while CLR is low.
X
X
X
X
1
Sets all DAC output voltages to 0V
X
1
XXXXX
Invalid state with any other control line active
X
X
1
XXXX
Invalid state with any other control line active
X = Don’t care; ** = Don’t care; however, CS and WR1 = 1 will inhibit changes to the input registers.


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