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SP9602KS Datasheet(PDF) 5 Page - Sipex Corporation |
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SP9602KS Datasheet(HTML) 5 Page - Sipex Corporation |
5 / 11 page SP9602DS/02 SP9602 Dual, 12-Bit, Low Power Voltage Output D/A Converter © Copyright 1999 Sipex Corporation 5 bit mode, the four least significant bits (LSBs) are connected to the four most significant bits (MSBs), allowing an 8-bit MSB-justified interface. All data inputs are enabled using the CS signal in both modes. ThedigitalinputsaredesignedtobebothTTLand5V CMOS compatible. InordertoreducetheDACfullscaleoutputsensitivity to the large weighting of the MSB’s found in conven- tionalR-2Rresistorladders,the3MSB’saredecoded into 8 equally weighted levels. This reduces the contribution of each bit by a factor of 4, thus, reducing the output sensitivity to mismatches in resistors and switches by the same amount. Linearity errors and stability are both improved for the same reasons. Each D/A converter is separated from the data bus by two registers,eachconsistingoflevel-triggeredlatches, Figure 1. The first register (input register) is 12-bits wide.Theinputregisterisselectedbytheaddressinput A 0 and A1 and is enabled by the CS and WR1 signals. In the 8-bit mode, the enable signal to the 8 MSB’s is disabled by a logic low on B1/B2 to allow the 4 LSB’s to be updated. The second register (DAC register), accepts the decoded 3 MSB’s plus the 9 LSB’s. The two DAC registers are updated simulta- neously for both DAC’s using the XFER and WR2 signals. Using the CLR and WR2 signals or the power-on-reset,(enabledwhenthepowerisswitched on) the DAC registers are set to 1000 0000 0000 and the DAC outputs will settle to 0V. Usingthecontrollogicinputs,theuserhasfullcontrol of address decoding, chip enable, data transfer and clearing of the DAC’s. The control logic inputs are level triggered, and like the data inputs, are TTL and CMOS compatible. The truth table (Table 2) shows the appropriate functions associated with the states of the control logic inputs. The DACs themselves are implemented with a preci- sion thin–film resistor network and CMOS transmis- sion gate switches. Each D/A converter is used to convert the 12-bit input from its DAC register to a precision voltage. The bipolar voltage output of the SP9602 is created on-chip from the DAC Voltage Output (V DAC) by using an operational amplifier and two feedback resistors connected as shown in Figure 2. This configuration produces a +4.5V bipolar output range with standard offset binary coding (See Table 1.). THEORY OF OPERATION The SP9602 consists of five main functional blocks — the input data multiplexer, the data registers, control logic, two 12-bit D/A converters, and two bipolar output voltage amplifiers. The input data multiplexer is designed to interface to either 12- or 8- bitmicroprocessordatabusses. Theinputdataformat iscontrolledbytheB1/B2signal—alogic“1”selects the 12-bit mode, while a logic “0” selects the 8-bit mode. In the 12-bit mode the data is transferred to the input registers without changes in its format. In the 8- FEATURES The SP9602 is a very low power, dual version of the popular SP9345, Quad 12-Bit Digital-to-Ana- log Converter. This Dual, Voltage Output, 12-Bit Digital-to-Analog Converter features ±4.5V out- put swings when using ±5 volt supplies. The input codingformatusedisstandardoffsetbinary.(Please refer to Table 1 below.) The converter utilizes double-buffering on each of the 12 parallel digital inputs, for easy microproces- sor interface. Each 12-bit DAC is independently addressable and both DACS may be simulta- neously updated using a single XFER command. The output settling-time is specified at 30 µs to full 12–bit accuracy when driving a 5Kohm, 50pF load combination. The SP9602, Dual 12-Bit Digital-to- Analog Converter is ideally suited for applications suchasATE,processcontrollers,robotics,andinstru- mentation. TheSP9602 isavailablein28–pinplastic SOIC and plastic DIP packages, specified over the commercial (0 °C to +70°C) temperature range. Table 1. Offset Binary Coding INPUT OUTPUT MSB LSB 1111 1111 1111 V REF - 1 LSB 1111 1111 1110 V REF - 2 LSB 1000 0000 0001 0 + 1 LSB 1000 0000 0000 0 0000 0000 0001 -VREF + 1 LSB 0000 0000 0000 -V REF 1 LSB = 2VREF 212 |
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