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SP9840KS Datasheet(PDF) 7 Page - Sipex Corporation |
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SP9840KS Datasheet(HTML) 7 Page - Sipex Corporation |
7 / 10 page 263 a) b) Figure 2. a) Inverted Single–Quadrant Operation; b) 4–Quadrant Operation Applications which require two–quadrant operation with respect to pseudoground should use the SIPEX SP9841orSP9842two–quadrantmultiplyingDACs. The choice of voltage to use for the pseudoground is limitedbythelegalvoltageswingattheopampoutput. The op amp exhibits excellent linearity for output voltages between, conservatively, 100mV and V DD – 1.5V. The op amp BiCMOS output stage consists of annpnfollowerloadedbyanNMOScommonsourced to ground. This circuit exhibits wide bandwidth and can source large currents, while retaining the capabil- ity of driving the output to voltages close to ground. At output voltages below 25mV, feedback forces some op amp internal nodes toward the supply rails. The NMOS pull–down device gets driven hard and the NMOS device enters the linear region — it begins to function in the same manner as a 50 ohm resistor. In reality, the wideband amplifier output stage sinks some internal quiescent current even when driving the output towards ground. This sunk current drops across the output stage NMOS transistor ON– resistance and internal routing resistance to pro- vide a minimum output voltage below which the amplifier cannot drive. This minimum voltage is in the 15 to 25mV range. It varies within a package with each op amp's offset voltage and biasing variations. If an input voltage lower than this minimum, such as code 255 when V IN(X) is grounded, is requested, feedback within the op amp circuit will force internal nodes to the rails, while the output will remain saturated near this minimum value. Non–saturated monotonic be- havior returns between 25mV and 100mV at the output, but full open loop gain and linearity are not apparent until the output voltage is nearly 100mV above the negative supply. Four–quad- rant (programmable signed attenuator) applica- tions usually bias V REFL up at system pseudoground, well above this saturation re- gion, and therefore maintain linearity even at high attenuations (i.e. near code 80 HEX). Driving the Reference Inputs The eight independent V IN inputs of the SP9840, and the four–pair of inputs in the SP9843, exhibit a code– dependent input resistance, as shown in the specifica- tions, and as a typical graph. In general, these inputs should be driven by an amplifier capable of handling Table 2. Logic Control Input Truth Table. SDI CLK LOADH PRESETL LOGIC OPERATION X L L H No Change Data L H Shift In One Bit from SDI Shift Out 12–clock delayed data at SDO X X X L All DAC Registers Preset to 80 H (Note 1) X L H H Load Serial Register Data into DAC(X) Register Note 1: "Preset" may not persist at all DACs if LOADH is high when PRESETL returns high. |
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