MDT2010(IB)

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P. 5

2005/6 VER1.3

7. Reset Condition for all Registers

Register

Address

Power-On Reset

/MCLR or WDT Reset

CPIO A

－－

1111 1111

1111 1111

CPIO B

－－

1111 1111

1111 1111

TMR

－－

--11 1111

--11 1111

IAR

00h

－

－

RTCC

01h

xxxx xxxx

uuuu uuuu

PC

02h

1111 1111

1111 1111

STATUS

03h

0001 1xxx

000# #uuu

MSR

04h

111x xxxx

111u uuuu

PORT A

05h

- - - - xxxx

- - - - uuuu

PORT B

06h

xxxx xxxx

uuuu uuuu

Note : u＝unchanged,

x＝unknown,

- ＝unimplemented, read as “0”

#＝value depends on the condition of the following table

Condition

Status: bit 4

Status: bit 3

/MCLR reset (not during SLEEP)

u

u

/MCLR reset during SLEEP

1

0

WDT reset (not during SLEEP)

0

1

WDT reset during SLEEP

0

0

8. Instruction Set

Instruction Code

Mnemonic

Operands

Function

Operating

Status

010000 00000000

NOP

No operation

None

010000 00000001

CLRWT

Clear Watchdog timer

0→WT

TF, PF

010000 00000010

SLEEP

Sleep mode

0→WT, stop OSC TF, PF

010000 00000011

TMODE

Load W to TMODE register

W→TMODE

None

010000 00000100

RET

Return

Stack→PC

None

010000 00000rrr

CPIO

R

Control I/O port register

W→CPIO

r

None

010001 1rrrrrrr

STWR

R

Store W to register

W→R

None

011000 trrrrrrr

LDR R, t

Load register

R→t

Z

111010 iiiiiiii

LDWI

I

Load immediate to W

I→W

None