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DP8521AV-20 Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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DP8521AV-20 Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 70 page  20 Signal Descriptions (Continued) Pin Device (If not Input Description Name applicable to all) Output 23 REFRESH SIGNALS RFIP(RFRQ)O REFRESH IN PROGRESS or REFRESH REQUEST When ECAS0 is asserted during programming this output functions as RFIP and is asserted prior to a refresh cycle and is negated when all the RAS outputs are negated for that refresh When ECAS0 is negated during programming this output functions as RFRQ When asserted this pin specifies that 13 msor15 ms have passed If DISRFSH is negated the DP8520A21A22A will perform an internal refresh as soon as possible If DISRFRSH is asserted RFRQ can be used to externally request a refresh through the input RFSH This output has a high capacitive driver and a 20X series damping resistor RFSH I REFRESH This input asserted with DISRFRSH already asserted will request a refresh If this input is continually asserted the DP8520A21A22A will perform refresh cycles in a burst refresh fashion until the input is negated If RFSH is asserted with DISRFSH negated the internal refresh address counter is cleared (useful for burst refreshes) DISRFSH I DISABLE REFRESH This input is used to disable internal refreshes and must be asserted when using RFSH for externally requested refreshes 24 PORT A ACCESS ADS I ADDRESS STROBE or ADDRESS LATCH ENABLE Depending on programming this input can function as ADS or ALE In mode 0 the input (ALE) I functions as ALE and when asserted along with CS causes an internal latch to be set Once this latch is set an access will start from the positive clock edge of CLK as soon as possible In Mode 1 the input functions as ADS and when asserted along with CS causes the access RAS to assert if no other event is taking place If an event is taking place RAS will be asserted from the positive edge of CLK as soon as possible In both cases the low going edge of this signal latches the bank row and column address if programmed to do so CS I CHIP SELECT This input signal must be asserted to enable a Port A access AREQ I ACCESS REQUEST This input signal in Mode 0 must be asserted some time after the first positive clock edge after ALE has been asserted When this signal is negated RAS is negated for the access In Mode 1 this signal must be asserted before ADS can be negated When this signal is negated RAS is negated for the access WAIT O WAIT or DTACK This output can be programmed to insert wait states into a CPU access cycle With R7 negated during programming the output will function (DTACK)O as a WAIT type output In this case the output will be active low to signal a wait condition With R7 asserted during programming the output will function as DTACK In this case the output will be negated to signify a wait condition and will be asserted to signify the access has taken place Each of these signals can be delayed by a number of positive clock edges or negative clock levels of CLK to increase the microprocessor’s access cycle through the insertion of wait states WAITIN I WAIT INCREASE This input can be used to dynamically increase the number of positive clock edges of CLK until DTACK will be asserted or WAIT will be negated during a VRAM access 25 PORT B ACCESS SIGNALS AREQB DP8522A I PORT B ACCESS REQUEST This input asserted will latch the row column and bank address if programmed and requests an access to take place for Port B If only the access can take place RAS will assert immediately If the access has to be delayed RAS will assert as soon as possible from a positive edge of CLK ATACKB DP8522A O ADVANCED TRANSFER ACKNOWLEDGE PORT B This output is asserted when the access RAS is asserted for a Port B access This signal can be used to only generate the appropriate DTACK or WAIT type signal for Port B’s CPU or bus 8 |
Similar Part No. - DP8521AV-20 |
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Similar Description - DP8521AV-20 |
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