The output capacitor values are generally determined by

the ESR and voltage rating requirements rather than capaci-

tance requirements for stability. Low ESR capacitors that meet

the ESR requirement usually have more output capacitance than

required for stability. Only specialized low-ESR capacitors in-

tended for switching-regulator applications, such as AVX TPS,

Sprague 595D, Sanyo OS-CON, Nichicon PL series or Kemet

T510 series should be used. The capacitor must meet mini-

mum capacitance and maximum ESR values as given in the

following equations:

2.5V

APPLICATION NOTES

CURRENT LIMITING:

The MSK 5040 is equipped with a pair of sense pins that

are used to sense the load current using an external resistor

(Rs). The current-limit circuit resets the main PWM latch and

turns off the internal high-side MOSFET switch whenever the

voltage difference between Sense High and Sense Low ex-

ceeds 100mV. This limiting occurs in both current flow direc-

tions, putting the threshold limit at ±100mV. The tolerance

on the positive current limit is ±20%. The external low-value

sense resistor must be sized for 80mV/Rs to guarantee enough

load capacity. Load components must be designed to with-

stand continuous current stresses of 120mV/Rs.

For very high-current applications, it may be useful to wire

the sense inputs with a twisted pair instead of PCB traces.

This twisted pair needn't be anything unique, perhaps two pieces

of wire-wrap wire twisted together. Low inductance current

sense resistors, such as metal film surface mount styles are

best.

SOFT START/Cton:

The internal soft-start circuitry allows a gradual increase of

the internal current-limit level at start-up for the purpose of

reducing input surge currents, and possibly for power-supply

sequencing. In Disable mode, the soft-start circuit holds the

Cton capacitor discharged to ground. When Enable goes high,

a 4µA current source charges the Cton capacitor up to 3.2V.

The resulting linear ramp causes the internal current-limit thresh-

old to increase proportionally from 20mV to 100mV. The out-

put capacitors charge up relatively slowly, depending on the

Cton capacitor value. The exact time of the output rise de-

pends on output capacitance and load current and is typically

1mS per nanofarad of soft-start capacitance. With no capaci-

tor connected, maximum current limit is reached typically within

10µS.

ENABLE FUNCTION:

The MSK 5040 is enabled by applying a logic level high to

the Enable pin. A logic level low will disable the device and

quiescent input current will reduce to approximately 2mA. The

Enable threshold voltage is 1V.

If automatic start up is re-

age is +36V.

INPUT CAPACITOR SELECTION:

OUTPUT CAPACITOR SELECTION:

These equations provide 45 degrees of phase margin to

ensure jitter-free fixed-frequency operation and provide a damped

output response for zero to full-load step changes. Lower qual-

ity capacitors can be used if the load lacks large step changes.

Bench testing over temperature is recommended to verify ac-

ceptable noise and transient response.

As phase margin is

reduced, the first symptom is timing jitter, which shows up in

the switching waveforms. Technically speaking, this typically

harmless jitter is unstable operation, since the switching fre-

quency is non-constant. As the capacitor ESR is increased,

the jitter becomes worse. Eventually, the load-transient wave-

form has enough ringing on it that the peak noise levels exceed

the output voltage tolerance. With zero phase margin and in-

stability present, the output voltage noise never gets much

industrial temperature range digital systems can usually multi-

ply the calculated ESR value by a factor of 1.5 without hurting

stability or transient response.

The output ripple is usually dominated by the ESR of the

Including the capacitive term, the full equation for ripple in the

πfC)). In

idle mode, the inductor current becomes discontinuous with

high peaks and widely spaced pulses, so the noise can actually

be higher at light load compared to full load. In idle mode, the

output ripple can be calculated as follows:

Rev. F 2/06

3

POWER DISSIPATION:

In high current applications, it is very important to ensure

that both MOSFETS are within their maximum junction tem-

perature at high ambient temperatures. Temperature rise can

be calculated based on package thermal resistance and worst

case dissipation for each MOSFET. These worst case dissipa-

tions occur at minimum voltage for the high side MOSFET and

at maximum voltage for the low side MOSFET.

Calculate power dissipation using the following formulas:

During output short circuit, Q2, the synchronous-rectifier

MOSFET, will have an increased duty factor and will see addi-

tional stress. This can be calculated by:

Q2 DUTY=1-

The MSK 5040 has an internal high frequency ceramic ca-

Connect a low-ESR

bulk capacitor directly to the input pin of the MSK 5040. Se-

lect the bulk input filter capacitor according to input ripple-

current requirements and voltage rating, rather than capacitor

value.

Electrolytic capacitors that have low enough ESR to

meet the ripple-current requirement invariably have more than

adequate capacitance values.

Aluminum-electrolytic capaci-

tors are preferred over tantalum types, which could cause power-

up surge-current failure when connecting to robust AC adapt-

ers or low-impedance batteries. RMS input ripple current is

determined by the input voltage and load current, with the

RDS= 0.060

Ω MAX at 25°C

RDS= 0.120

Ω MAX at 150°C