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CY26126
Advance Information
Document #: 38-07351 Rev. *A
Page 3 of 5
Note:
3.
Not 100% tested.
AC Electrical Characteristics (VDD = 3.3V)
[3]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of VDD
45
50
55
%
t3
Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDD
0.8
1.4
V/ns
t4
Falling Edge Slew
Rate
Output Clock Fall Time, 80% - 20% of VDD
0.8
1.4
V/ns
t9
Clock Jitter
Peak to Peak period jitter
200
ps
t10
PLL Lock Time
3ms
Test Circuit
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY26126SC
S8
8-Pin SOIC
Commercial
3.3V
0.1
µF
VDD
0.1
µF
VDD
CLK out
CLOAD
GND
OUTPUTS
t1
t2
CLK
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
CLK
80%
20%
t4
Figure 2. Rise and Fall Time Definitions
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