FLASH MEMORY

9

K9K2G08R0A

K9K2G08U0A

Product Introduction

The K9K2G08X0A is a 2112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2112x8 columns. Spare 64 col-

umns are located from column address of 2048~2111. A 2112-byte data register is connected to memory cell arrays for accommodat-

ing data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array is

made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block

consists of two NAND structures. A NAND structure consists of 32 cells. Total 135,168 NAND cells reside in a block. The program and

read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of

2048 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K2G08X0A.

The K9K2G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades

to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by

bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For

example, Reset Command, Status Read Command and etc require just one cycle bus. Some other commands, like Page Read, Block

Erase and Page Program, require two cycles: one cycle for setup and the other cycle for execution. The 264M byte physical space

requires 29 addresses, thereby requiring five cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that order.

Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation,

however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command

register. Table 1 defines the specific commands of the K9K2G08X0A.

Table 1. Command Sets

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Cache program and Copy-Back program are supported only with 3.3V device.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

Function

1st. Cycle

2nd. Cycle

Acceptable Command during Busy

Read

00h

30h

Read for Copy Back

00h

35h

Read ID

90h

-

Reset

FFh

-

O

Page Program

80h

10h

Cache Program

80h

15h

Copy-Back Program

85h

10h

Block Erase

60h

D0h

85h

-

05h

E0h

Read Status

70h

O