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SN74LV4040ADR Datasheet(PDF) 5 Page - Texas Instruments |
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SN74LV4040ADR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 12 page www.ti.com APPLICATION INFORMATION VCC VDEMOUT (AV) 1/2 V CC 0 φDEMOUT –3605 05 3605 VCC V DEMOUT (AV) 1/2 V CC 0 φDEMOUT 05 905 1805 VCC GND SIGIN COMPIN VCOOUT PC1OUT VCOIN SIGIN COMPIN VCOOUT PC2 OUT VCOIN VCC GND PCPOUT High-Impedance Off State SIGIN COMPIN VCOOUT PC3OUT VCOIN VCC GND 0 fDEMOUT 05 1805 3605 1/2 VCC VDEMOUT(AV) VCC SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO SCES656A – FEBRUARY 2006 – REVISED FEBRUARY 2006 AVERAGE OUTPUT VOLTAGE AVERAGE OUTPUT VOLTAGE vs vs INPUT PHASE DIFFERENCE INPUT PHASE DIFFERENCE Figure 1. Phase Comparator 1: Figure 2. Phase Comparator 2: VDEMOUT = VPC1OUT = (VCC/π) (SIGIN – COMPIN); VDEMOUT = VPC2OUT = (VCC/4) (SIGIN – COMPIN); DEMOUT = (SIGIN – COMPIN) DEMOUT = (SIGIN – COMPIN) Figure 3. Typical Waveforms for PLL Using Figure 4. Typical Waveforms for PLL Using Phase Comparator 1, Loop Locked at fo Phase Comparator 2, Loop Locked at fo AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE Figure 5. Phase Comparator 3: Figure 6. Typical Waveforms for PLL Using VDEMOUT = VPC3OUT = (VCC/2π) (SIGIN – COMPIN); Phase Comparator 3, Loop Locked at fo DEMOUT = (SIGIN – COMPIN) 5 Submit Documentation Feedback |
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