M65617SP datasheet(3/15 Pages) MITSUBISHI

Part #	M65617SP

Description	PICTURE-IN-PICTURE SIGNAL PROCESSING

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

Direct Link	http://www.mitsubishichips.com

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MITSUBISHI ICs (TV)

M65617SP

PICTURE-IN-PICTURE SIGNAL PROCESSING

3

DESCRIPTION OF PIN

Pin No.

Name

I/O

Function

Remarks

1

AVss3 (VCXO)

GND

Grounding (analog burst lock PLL section)

2

VCXO out

O

Oscillation output signal

3

VCXO in

I

Oscillation input signal

4

FILTER

O

Filter

5

BIAS

O

Bias

6

AVdd3 (VCXO)

Vdd

Power supply (analog burst lock PLL section)

7

AVdd2 (m)

Vdd

Power supply (analog main signal A/D section)

8

Vin (m)

I

Main color input signal

9

Vrt (m)

O

Main signal A/D reference voltage output +

10

Vrb (m)

O

Main signal A/D reference voltage output -

11

AVss2 (m)

GND

Grounding (analog main signal A/D section)

12

AVdd1 (s)

Vdd

Power supply (analog sub-signal A/D section)

13

Vin (s)

I

Sub-composite video input signal

14

Vrt (s)

O

Sub-signal A/D reference voltage output +

15

Vrb (s)

O

Sub-signal A/D reference voltage output -

16

AVss1 (s)

GND

Grounding (analog sub-signal A/D section)

17

RESET

I

Power-ON reset input signal.

Connected to the power supply with

100k

Ω, and grounded with 10µF

18

DVss1

GND

Grounding (digital section)

19

DVdd1

Vdd

Power supply (digital section)

20

BGP(s)/TEST0

(I/)O

Sub-screen burst gate pulse output

Open

21

SCK

I

Sub-screen 4fsc clock input

Grounding

22

CSYNC(s)/TEST1

I(/O)

Sub-screen CSYNC input

Pulldown 15k

Ω

23

ACK

O

I2C bus data/acknowledge output signal

24

DATA

I

I2C bus data input signal

25

CLK

I

I2C bus clock input signal

26

DVss2

GND

Grounding (digital section)

27

DVdd2

Vdd

Power supply (digital section)

28

BGP(m)/TEST2

(I/)O

For testing

Open

29

fsc/TEST3

I(/O)

For testing

Pulldown 15k

Ω

30

MCK

I

For testing

Grounding

31

SWM/TEST4

(I/)O

For testing

Open

32

HD/TEST5

I(/O)

Horizontal sync input signal

33

VD/CSYNC/

TEST6

I(/O)

Vertical sync input signal

34

SWMG/TEST7

I(/O)

Sub-screen display authorization input signal

Pullup 15k

Ω

35

DVdd3 (ram)

Vdd

Power supply (digital RAM section)

36

DVss3 (ram)

GND

Grounding (digital RAM section)

37

Cout-sub

O

Sub-screen color signal D/A output signal

38

ADJ-Csub

O

For adjustment of sub-screen color signal D/A

39

Yout-sub

O

Sub-screen luminance signal D/A output signal

40

ADJ-Ysub

O

For adjustment of sub-screen luminance signal D/A

41

Y-PIPin

I

Sub-screen luminance signal re-input signal

42

AVss4 (da)

GND

Grounding (analog D/A and SW sections)

43

C-PIPin

I

Sub-screen color signal re-input signal

44

AVdd4 (da)

Vdd

Power supply (analog D/A & SW sections)

45

C-PIP

O

PIP color signal output signal

46

TEST8

I

For testing

Pullup 15k

Ω

47

Y-PIP

O

PIP luminance signal output signal

48

TEST9

I

For testing

Grounding

49

Yin

I

Main luminance input signal

50

TESTEN

I

For testing

Grounding

51

Cin

I

Main color input signal

52

AVssf (ana)

Vss

Grounding (analog section)

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M65617SP Datasheet(PDF) 3 Page - Mitsubishi Electric Semiconductor

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