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SMH4804 Datasheet(PDF) 3 Page - Summit Microelectronics, Inc. |
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SMH4804 Datasheet(HTML) 3 Page - Summit Microelectronics, Inc. |
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3 / 41 page  SMH4804 Functional Description Summit Microelectronics 2050 3.7 10/30/02 3 –\ FUNCTIONAL DESCRIPTION The SMH4804 integrated hot swap power controller operates within a wide supply range, typically -32 to -72 volts, and generates the signals necessary to drive isolated- output DC/DC converters. The general start-up procedure is as follows: • A physical connection must first be made with the chassis to discharge any electrostatic voltage potentials when a typical add-in board is inserted into the powered backplane. • The board then contacts the long pins on the backplane that provide power and ground. • As soon as power is applied the device starts up, but does not immediately apply power to the output load. • Under-voltage and over-voltage circuits inside the controller verify that the input voltage is within a user- specified range. • The SMH4804 senses the PD1# and PD2# pin detection signals to indicate the card is seated properly. These requirements must be met for a Pin Detect Delay period of tPDD. Once this time has elapsed, the hot-swap controller enables VGATE to turn on the external power MOSFET switch. The VGATE output is current limited to IVGATE, allowing the slew rate to be easily modified using external passive components. During the controlled turn-on period the VDS of the MOSFET is monitored by the drain sense input. When DRAIN SENSE drops below 2.5V, and VGATE rises above VDD – VGT, the SMH4804 asserts the PG1# through PG4# power good outputs to enable the DC/ DC controllers. The ENPGA, ENPGB, and ENPGC Power Good Enable inputs may be used to activate or deactivate specific output loads. Steady-state operation is maintained as long as all conditions are normal. Any of the following events may cause the device to disable the DC/DC controllers by shutting down the power MOSFET: • an under-voltage or over-voltage condition on the host power supply. • an over-current event detected on the CBSENSE input • a failure of the power MOSFET sensed via the DRAIN SENSE pin. • the PD1#/PD2# pin detect signals becoming invalid. • the master enable (EN/TS) falls below 2.5V. • the FS# input is driven low by events on the secondary side of the DC/DC controllers. The SMH4804 may be configured so that after any of these events occurs, the VGATE output shuts off and either latches into an off state, or recycles power after a cooling down period, tCYC. Powering V DD The SMH4804 contains an internal shunt regulator on the VDD pin that prevents the voltage from exceeding 12V. It is necessary to use a dropper resistor (RD) between the host power supply and the VDD pin in order to limit current into the device and prevent possible damage. The dropper resistor allows the device to operate across a wide range of system supply voltages, typically -32 V to -72V, and also helps protect the device against common-mode power surges. Refer to the Applications Section for help on calculating the RD resistance value. Hot-Swap Verification There are several enabling inputs that allow the host to control the SMH4804. The Pin Detect signals (PD1# and PD2#) are two active low enables that are generally used to indicate that the add-in circuit card is properly seated. These inputs must be held low for a pin-detect delay period of tPDD before a power-up sequence may be initiated. This is typically done by clamping the inputs to VSS through the implementation of an ejector switch, or alternatively through the use of staggered pins at the card-cage interface. The pin detect delay (tPDD) timing parameter is controlled by bits 1:0 of register 9. Refer to Register 9 - Address 1001 on page 38 for more information. Two shorter pins, arranged at opposite ends of the connector, force the card to be fully seated before both pin detects are enabled. Care must be taken not to exceed the maximum voltage rating of these pins during the insertion process. Refer to details in the Applications Section for proper circuit implementation. Note that the PD1# and PD2# inputs are enabled or disabled using bit 0 of Register 3. Refer to Register 3 - Address 0011 on page 32 for more information. The EN/TS input provides an active high comparator input that may be used as a master enable or temperature sense input. This input signal must exceed 2.5V (nominal) for proper operation. Refer to the Pin Descriptions on page 10 for more information. Under-/Over-Voltage Sensing The Under-Voltage (UV) and Over-Voltage (OV) inputs provide a set of comparators that act in conjunction with an external resistive divider ladder to sense whether or not the host supply voltage is within the user-defined limits. The power-up sequence is initiated when the input to the UV pin rises above 2.5V and the input to the OV pin falls below |
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