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SMM766FR0 Datasheet(PDF) 9 Page - Summit Microelectronics, Inc.

Part # SMM766FR0
Description  Six-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link?
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Manufacturer  SUMMIT [Summit Microelectronics, Inc.]
Direct Link  http://www.summitmicro.com
Logo SUMMIT - Summit Microelectronics, Inc.

SMM766FR0 Datasheet(HTML) 9 Page - Summit Microelectronics, Inc.

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SMM766
Preliminary Information
Summit Microelectronics, Inc
2086 2.1 12/13/2005
9
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Internally regulated to 3.6V
0.8 x
VDD_CAP
V
VIH
Input high voltage (MR#, SDA,
SCL, PWR_ON, SEQ_LINK,
FS#)
3
Internally regulated to 5.5V
0.7 x
VDD_CAP
V
Internally regulated to 3.6V
0.2 x
VDD_CAP
V
VIL
Input low voltage (MR#, SDA,
SCL, PWR_ON, SEQ_LINK,
FS#)
3
Internally regulated to 5.5V
0.3 x
VDD_CAP
V
VOL
Open drain outputs (RST#,
FS#, PWR_ON, HEALTHY,
FAULT#, PUPx, SEQ_LINK)
ISINK = 1mA
0
0.4
V
IOL
Output low current
Note – Total ISINK from all PUPx pins
should not exceed 6mA or ADOCACC
specification will be affected
0
1.0
mA
VSENSE
Positive sense voltage
VM pin
+0.3
VDD_CAP
V
VMONITOR
Monitor threshold step size
VM, AIN1/AIN2 pins
5
mV
Commercial temp range
-3
+3
oC
tSA
Internal temperature sensor
accuracy
Industrial temp range
-5
+5
oC
tMONITOR
Temperature threshold step
size
Internal temp sensor
0.25
oC
VREF
Internal 1.25VREF output
voltage
1.24
1.25
1.26
V
–40
°C to +85°C
-0.25
+0.25
%
VREF TC
Internal VREF temperature
coefficient
–5
°C to +70°C
-0.15
+0.15
%
VREF ACC
Internal VREF accuracy
-0.4
+0.4
%
Ext VREF
External VREF voltage range
0.5
VDD_CAP
V
External VREF=1.25V, ±0.1%,
total PUPx ISINK < 3ma, VSENSE
< 3.5V
-0.2
0.1
+0.2
%
External VREF=1.25V, ±0.1%,
total PUPx ISINK < 3ma, VSENSE
> 3.5V
-0.5
0.3
+0.5
%
ADOCACC
ADOC (Active DC Output
Control)/margin accuracy
Internal VREF=1.25V, total
PUPx ISINK < 3ma
-0.5
0.3
+0.5
%
VOUT_VALID
Minimum output valid voltage
VDD_CAP voltage at which
the PUP, RST#, HEALTHY
and FAULT#, FS#, PWR_ON
SEQ_LINK, outputs are valid
1
V
VDD_CAP rising
2.6
V
UVLO
UVLO (Under Voltage Lockout)
threshold
4
VDD_CAP falling
2.5
V
Note 1 – Range depends on internal regulator set to 3.6V or 5.5V see 12VIN specification.
Note 2 – See Application Note 37 which describes the type of capacitors to use to obtain minimum leakage.
Note 3 – All logic levels are derived with respect to the voltage present on VDD_CAP, when supplied from the VDD input VDD_CAP is equal to
VDD, under no load.
Note 4 – (100mV typ Hysteresis)


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