Electronic Components Datasheet Search |
|
IDTCSPF2510CPG Datasheet(PDF) 4 Page - Integrated Device Technology |
|
IDTCSPF2510CPG Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 8 page 4 0ºC TO 85ºC TEMPERATURE RANGE IDTCSPF2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING FREE-AIR TEMPERA- TURE RANGE (UNLESS OTHERWISE NOTED) Symbol Test Conditions VDD Min. Typ. Max. Unit VIH Input HIGH Level 2 V VIL Input LOW Level 0.8 V VIK II = -18mA 3V – 1.2 V IOH = -100 µA Min. to Max. VDD – 0.2 VOH IOH = -12mA 3V 2.1 V IOH = -6mA 3V 2.4 IOL = 100 µA Min. to Max. 0.2 VOH IOL = 12mA 3V 0.8 V IOL = 6mA 3V 0.55 II VI = VDD or GND 3.6V ±5 µA IDD VI = VDD or GND, AVDD = GND, IO = 0, Outputs: LOW or HIGH 3.6V 10 µA ∆IDD One input at VDD - 0.6V, other inputs at VDD or GND 3.3V to 3.6V 500 µA CPD PowerDissipationCapacitance 3.6V 10 14 pF IDDA (2) AVDD Power Supply Current AVDD = 3.3V 10 mA NOTES: 1. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions. 2. For IDD of AVDD, see TYPICAL CHARACTERISTICS. Min. Max. Unit Clockfrequency 25 140 MHz fCLOCK Input clock duty cycle 40% 60% Stabilizationtime(1) 1ms TIMING REQUIREMENTS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. SWITCHING CHARACTERISTICS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 25pF VDD = 3.3V ± 0.165V VDD = 3.3V ± 0.3V Parameter (1) From (Input) To (Output) Min. Typ. Max. Min. Typ. Max. Unit tPHASE error (2) 100MHz < CLK ↑ < 133MHz FBIN ↑ –150 150 ps tPHASEerror–jitter(2,4) CLK ↑ = 133MHz FBIN ↑ – 50 50 ps tSK(o)(3) Any Y (133MHz) Any Y 150 ps Jitter(cycle-cycle) CLK = 66MHz to 133MHz Any Y or FBOUT | 70 | ps (peak-to-peak) CLK = 100MHz to 133MHz Any Y or FBOUT | 65 | ps Duty cycle reference (5) CLK = 133MHz Any Y or FBOUT 45 55 % tR Any Y or FBOUT 1.3 1.9 0.8 2.1 ns tF Any Y or FBOUT 1.7 2.5 0.8 2.5 ns NOTES: 1. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 2. See PARAMETER MEASUREMENT INFORMATION. 3. The tSK(O) specification is only valid for equal loading of all outputs. 4. Phase error does not include jitter. 5. See TYPICAL CHARACTERISTICS. |
Similar Part No. - IDTCSPF2510CPG |
|
Similar Description - IDTCSPF2510CPG |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |