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K9K8G08U0A-P Datasheet(PDF) 8 Page - Samsung semiconductor |
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K9K8G08U0A-P Datasheet(HTML) 8 Page - Samsung semiconductor |
8 / 49 page FLASH MEMORY 8 K9WAG08U1A K9K8G08U0A Preliminary 2K Bytes 64 Bytes Figure 1. K9K8G08U0A Functional Block Diagram Figure 2. K9K8G08U0A Array Organization NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 2nd Cycle A8 A9 A10 A11 *L *L *L *L 3rd Cycle A12 A13 A14 A15 A16 A17 A18 A19 4th Cycle A20 A21 A22 A23 A24 A25 A26 A27 5th Cycle A28 A29 A30 *L *L *L *L *L VCC X-Buffers Command I/O Buffers & Latches Latches & Decoders Y-Buffers Latches & Decoders Register Control Logic & High Voltage Generator Global Buffers Output Driver VSS A12 - A30 A0 - A11 Command CE RE WE CLE WP I/0 0 I/0 7 VCC VSS 512K Pages (=8,192 Blocks) 2K Bytes 8 bit 64 Bytes 1 Block = 64 Pages (128K + 4k) Byte I/O 0 ~ I/O 7 1 Page = (2K + 64)Bytes 1 Block = (2K + 64)B x 64 Pages = (128K + 4K) Bytes 1 Device = (2K+64)B x 64Pages x 8,192 Blocks = 8,448 Mbits Row Address Page Register ALE 8,192M + 256M Bit NAND Flash ARRAY (2,048 + 64)Byte x 524,288 Y-Gating Row Address Column Address Column Address Row Address Data Register & S/A |
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