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X5114LI Datasheet(PDF) 4 Page - Xicor Inc. |
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X5114LI Datasheet(HTML) 4 Page - Xicor Inc. |
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4 / 40 page  X5114 4 The master will always initiate data transfers and provide the clock for both transmit and receive operations. The X5114 is considered a slave for all operations. The X5114 has special addressing mechanisms to allow up to 255 devices (or more after using the NOP command) to reside on one SPI communication bus. This reduces the number of bus lines required to talk to multiple X5114 devices. Communication to the device begins with a start condition. This consists of the falling edge of CSa or CSb. Following a CSa/CSb HIGH to LOW, the master selects one of many X5114 devices on the SPI bus, by transmitting a slave address (Software Device Addressing) or selects the only device on the bus using the CSa/CSb signal (Hardware Device Addressing). Software Device Addressing Mode In this device addressing mode, each X5114 has a unique slave address externally specified by the A7-A0 pins. The first byte transmitted to the device contains the device address. This address is compared with the external address pins, A7-A0. If matched, the device performs the task specified by the Instruction opcode sent in the next byte. If there is no match, the X5114 returns to the standby state. Device Address (Software Addressing only) DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 MSB LSB FIGURE 1. SPI Communications - Addressing Modes (Read example) CSO Software Addressed: D D D D D D D D O O O O CSa/CSb SCKa/SCKb SIa/SIb SOa/SOb Device Address Instruction Data In O O O O D D D D D D D D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 S S S S S S S S 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Don’t Care Status Data Out CSO D D D D D D D D CSa/CSb SCKa/SCKb SIa/SIb SOa/SOb Instruction Data In S S S S S S S S 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Don’t Care Status Data Out Hardware Addressed: A A A A A A A A P P P P P P P P O O O O O O O O 7 6 5 4 3 2 1 0 P P P P P P P P |
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