IDT71V3548S100BGI datasheet(5/26 Pages) IDT

Part #	IDT71V3548S100BGI

Description	256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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5 / 26 page

6.42

IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with

ZBT

™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

5

1

2

3

4567

A

VDDQ

A6

A4

NC(2)

A8

A16

VDDQ

B

NC

CE2

A3

ADV/

LD

A9

CE2

NC

C

A7

A2

VDD

A13

A17

NC

D

I/O8

NC

VSS

NC

VSS

I/O7

NC

E

NC

I/O9

VSS

NC

I/O6

F

VDDQ

NC

VSS

OE

VSS

I/O5

VDDQ

G

NC

I/O10

BW2

NC

I/O4

H

I/O11

NC

VSS

R/

W

VSS

I/O3

NC

J

VDDQ

VDD

VDDQ

K

NC

I/O12

VSS

CLK

VSS

NC

I/O2

L

I/O13

NC

BW1

I/O1

NC

M

VDDQ

I/O14

VSS

CEN

VSS

NC

VDDQ

N

I/O15

NC

VSS

A1

VSS

I/O0

NC

P

NC

I/OP2

VSS

A0

VSS

NC

I/OP1

R

NC

A5

LBO

VDD

A12

T

NC

A10

A15

NC

A14

A11

NC/ZZ(5)

U

VDDQ

5296 drw 13

NC

DD(1)

VNC

VSS

CE1

NC(2)

VDD(1)

,

NC/TMS(3)

NC/

TRST(3,4)

NC/TDO(3)

NC/TCK(3)

NC/TDI(3)

Pin Configuration - 256K x 18, 119 BGA

Top View

NOTES:

1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is

≥ VIH.

2. G4 and A4 are reserved for future 8M and 16M respectively.

3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.

4.

TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. Pin T7 supports ZZ (sleep mode) on the latest die revision.

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IDT71V3548S100BGI Datasheet(PDF) 5 Page - Integrated Device Technology

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