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K6F2016U4G-XF70 Datasheet(PDF) 6 Page - Samsung semiconductor |
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K6F2016U4G-XF70 Datasheet(HTML) 6 Page - Samsung semiconductor |
6 / 10 page Revision 0.0 CMOS SRAM April 2005 K6F2016U4G Family - 6 - Preliminary AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): CL= 100pF+1TTL CL= 30pF+1TTL CL1) 1. Including scope and jig capacitance R22) R12) VTM3) 2. R1=3070 Ω, R2=3150Ω 3. VTM =2.8V AC CHARACTERISTICS ( Vcc=2.7~3.3V, Industrial product:TA=-40 to 85°C ) Parameter List Symbol Speed Units 55ns 70ns Min Max Min Max Read Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO - 55 - 70 ns Output enable to valid output tOE - 25 - 35 ns UB, LB Access Time tBA - 55 - 70 ns Chip select to low-Z output tLZ 10 - 10 - ns UB, LB enable to low-Z output tBLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5- 5 - ns Chip disable to high-Z output tHZ 0 20 0 25 ns UB, LB disable to high-Z output tBHZ 0 20 0 25 ns Output disable to high-Z output tOHZ 0 20 0 25 ns Output hold from address change tOH 10 - 10 - ns Write Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address set-up time tAS 0- 0 - ns Address valid to end of write tAW 45 - 60 - ns UB, LB Valid to End of Write tBW 45 - 60 - ns Write pulse width tWP 40 - 50 - ns Write recovery time tWR 0- 0 - ns Write to output high-Z tWHZ 0 20 0 20 ns Data to write time overlap tDW 25 - 30 - ns Data hold from write time tDH 0- 0 - ns End write to output low-Z tOW 5- 5 - ns DATA RETENTION CHARACTERISTICS 1. 1) CS ≥Vcc-0.2V(CS controlled) or 2) LB=UB ≥Vcc-0.2V, CS≤0.2V(LB/UB controlled) Item Symbol Test Condition Min Typ Max Unit Vcc for data retention VDR CS ≥Vcc-0.2V1), VIN≥0V 1.5 - 3.3 V Data retention current IDR Vcc=1.5V, CS ≥Vcc-0.2V1), VIN≥0V - - 3 µA Data retention set-up time tSDR See data retention waveform 0- - ns Recovery time tRDR tRC - - |
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