TM4100GAD8

4194304 BY 8-BIT DRAM MODULE

SMMS508C – MARCH 1992 – REVISED JUNE 1995

4

POST OFFICE BOX 1443

capacitance over recommended ranges of supply voltage and operating free-air temperature,

f = 1 MHz

PARAMETER

MIN

MAX

UNIT

Ci(A)

Input capacitance, A0 – A10

40

pF

Ci(RC)

Input capacitance, CAS and RAS

56

pF

Ci(W)

Input capacitance, W

56

pF

CO

Output capacitance (pins DQ1 – DQ8)

12

pF

NOTE 5: VCC = 5 V ± 0.5 V and the bias on the pin under test is 0 V.

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature

PARAMETER

’4100GAD8-60

’4100GAD8-70

’4100GAD8-80

UNIT

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tAA

Access time from column address

30

35

40

ns

tCAC

Access time from CAS low

15

18

20

ns

tCPA

Access time from column precharge

35

40

45

ns

tRAC

Access time from RAS low

60

70

80

ns

tCLZ

CAS to output in low impedance

0

0

0

ns

tOFF

Output disable time after CAS high (see Note 6)

0

15

0

18

0

20

ns

NOTE 6: tOFF is specified when the output is no longer driven.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

’4100GAD8-60

’4100GAD8-70

’4100GAD8-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tRC

Cycle time, random read or write (see Note 7)

110

130

150

ns

tPC

Cycle time, page-mode read or write (see Note 8)

40

45

50

ns

tCHR

Delay time, RAS low to CAS high (CBR refresh only)

15

15

20

ns

tCRP

Delay time, CAS high to RAS low

0

0

0

ns

tCSH

Delay time, RAS low to CAS high

60

70

80

ns

tCSR

Delay time, CAS low to RAS low (CBR refresh only)

10

10

10

ns

tRAD

Delay time, RAS low to column address (see Note 10)

15

30

15

35

15

40

ns

tRAL

Delay time, column address to RAS high

30

35

40

ns

tCAL

Delay time, column address to CAS high

30

35

40

ns

tRCD

Delay time, RAS low to CAS low (see Note 10)

20

45

20

52

20

60

ns

tRPC

Delay time, RAS high to CAS low

0

0

0

ns

tRSH

Delay time, CAS low to RAS high

15

18

20

ns

tCAH

Hold time, column address after CAS low

10

15

15

ns

tDHR

Hold time, data after RAS low (see Note 9)

50

55

60

ns

tDH

Hold time, data

10

15

15

ns

tAR

Hold time, column address after RAS low (see Note 9)

50

55

60

ns

NOTES:

7. All cycle times assume tT = 5 ns.

8. To assure tPC min, tASC should be ≥ tCP.

9. The minimum value is measured when tRCD is set to tRCD min as a reference.

10. The maximum value is specified only to assure access time.