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VSC8021 Datasheet(PDF) 4 Page - Vitesse Semiconductor Corporation |
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VSC8021 Datasheet(HTML) 4 Page - Vitesse Semiconductor Corporation |
4 / 17 page VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8021/VSC8022 2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset Page 4 G52028-0, Rev 4.1 05/25/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com VSC8021 Multiplexer AC Characteristics (Over recommended operating conditions) Figure 3: VSC8021 Multiplexer Waveforms Table 1: VSC8021 Multiplexer AC Characteristics (over recommended operating conditions) NOTES: (1) The parts are guaranteed by design to operate from DC to a maximum frequency of 2.5GHz. (2) Required when SYNC not connected to ERR. Parameter Description Min Typ Max Units Conditions tC Clock period(1) 400 ps tD BYTE clock period (tD = tC x 8) 3.2 ns tDSU Parallel data set-up time 0.6 ns tDH Data hold time 1.4 ns tCMD High-speed clock output (CO, CON) timing, falling edge of CO to muxed data output, (DO, DON) timing 220 350 ps tBCLK8 Byte clock to CLK8 timing(2) 0.5 1.0 1.5 ns Jitter (p-p) CLKI, CLKIN to DO, DON (max-min), (HI to LO), same part, same pin at constant conditions <50 ps t D t C VALID DATA(2) tDH Serialized Byte 1 D01 D02 D03 D04 D05 D06 D07 D08 tDSU VALID DATA(1) tCMD NOTES: = Don’t care. period x 8 = period. CLKI (CLKIN) BYCLK (BYCLKN) (1) Negative edge is active edge. (2) BYCLK/CLK8 timing required when SYNC not connected to ERR. tBCLK8 High speed differential clock input D1-D8, D1N-D8N CO, CON DO,DON Byte clock input Parallel differential data inputs High speed differential clock outputs High speed differential data outputs SYNC CLK8 adjustment input CLKI , CLKIN (1) BYCLK (BYCLKN) (1) Phase adjustable ÷8 output CLK8 (2) |
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