3

ICS932S200

0427C—07/03/02

Frequency Select:

Note:

1. TCLK is a test clock driven on the x1 input during test mode.

ICS932S200 Power Management Features:

Note:

1. LOW means outputs held static LOW as per latency requirement next page.

2. On means active.

3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.

4. All 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled LOW.

5. IOAPIC, REF, 48 MHz signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions

except PD# = LOW

L

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