N16D1618LPA

Stock No. 23395- Rev L 1/06

5

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

Advance Information

NanoAmp Solutions, Inc.

Table 2: Pin Descriptions

PIN

PIN NAME

DESCRIPTIONS

CLK

System Clock

The system clock input. All other inputs are registered to the

SDRAM on the rising edge of the CLK

CKE

Clock Enable

Controls internal clock signal and when deactivated, the

SDRAM will be one of the states among power down, suspend

or self refresh.

/CS

Chip Select

Enable or disable all inputs except CLK, CKE and DQM

A11

Bank Address

Selects bank to be activated during /RAS activity

Selects bank to be read/written during /CAS activity

A0~A10

Address

Row Address : RA0~RA10

Column Address: CA0~CA7

Auto Precharge : A10

/RAS, /CAS, /WE

Row Address Strobe,

Column Address Strobe,

Write Enable

/RAS, /CAS and /WE define the operation

Refer function truth table for details

LDQM/UDQM

Data Input/Output Mask

Controls output buffers in read mode and masks input data in

write mode

DQ0~DQ15

Data Input/Output

Multiplexed data input/output pin

VDD/VSS

Power Supply/Ground

Power supply for internal circuits and input buffers

VDDQ/VSSQ

Data Output Power/Ground

Power Supply for output buffers

NC

No Connection

No Connection