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TC55NEM216ASTV55 Datasheet(PDF) 9 Page - Toshiba Semiconductor |
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TC55NEM216ASTV55 Datasheet(HTML) 9 Page - Toshiba Semiconductor |
9 / 12 page TC55NEM216ASTV55,70 2002-10-30 9/12 Note: (1) R/W remains HIGH for the read cycle. (2) If CE (or UB or LB ) goes LOW(or CS goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE (or UB or LB ) goes HIGH(or CS goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C) SYMBOL PARAMETER MIN TYP MAX UNIT VDH Data Retention Supply Voltage 2.0 5.5 V Ta = −40~40°C 3 IDDS2 Standby Current Ta = −40~85°C 20 µA tCDR Chip Deselect to Data Retention Mode Time 0 ns tR Recovery Time 5 ms CONTROLLED DATA RETENTION MODE CS CONTROLLED DATA RETENTION MODE (See Note 2) CE VDD 4.5 V GND VIH DATA RETENTION MODE tR (See Note 1) (See Note 1) tCDR VDD VDD − 0.2 V CE VDD 4.5 V GND VIL DATA RETENTION MODE tR tCDR 0.2 V VIH CS VDD |
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