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TSC8051C2XXXA12CCR Datasheet(PDF) 7 Page - TEMIC Semiconductors |
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TSC8051C2XXXA12CCR Datasheet(HTML) 7 Page - TEMIC Semiconductors |
7 / 28 page TSC8051C2 Rev. A (10 Jan. 97) 7 Preview MATRA MHS 6.1.2. Power Down Mode The instruction that sets PCON.1 is the last executed prior to entering power down. Once in power down, the oscillator is stopped. The contents of the onchip RAM and the Special Function Register are saved during power down mode. A hardware reset is the only way of exiting the power down mode. The hardware reset initiates the Special Function Register. In the Power Down mode, VCC may be lowered to minimize circuit power consumption. Care must be taken to ensure the voltage is not reduced until the power down mode is entered, and that the voltage is restored before the hardware reset is applied which frees the oscillator. Reset should not be released until the oscillator has restarted and stabilized. Table 1 describes the status of the external pins while in the power down mode. It should be noted that if the power down mode is activated while in external program memory, the port data that is held in the Special Function Register P2 is restored to Port 2. If the data is a 1, the port pin is held high during the power down mode by the strong pullup transistor. Table 1. Status of the external pins during Idle and Power Down modes. Mode Program Memory ALE PSEN Port 0 Port 1 Port 2 Port 3 PWMx Idle Internal 1 1 Port Data Port Data Port Data Port Data Floating Idle External 1 1 Floating Port Data Address Port Data Floating Power Down Internal 0 0 Port Data Port Data Port Data Port Data Floating Power Down External 0 0 Floating Port Data Port Data Port Data Floating 6.2. Stop Clock Mode Due to static design, the TSC8051C2 clock speed can be reduced down to 0 MHz without any data loss in memory or register. This mode allows step by step code execution, and permits to reduce system power consumption by bringing the clock frequency down to any value. When the clock is stopped, the power consumption is the same as in the Power Down Mode. 6.3. I/O Ports Structure The TSC8051C2 has four 8–bit ports. Each port consist of a latch (special function register P0 to P3), an input buffer and an output driver. These ports are the same as in 80C51, with the exception of the additional functions of port 1 and port 3 (see Pin Description section). 6.4. I/O Configurations Figure 4. shows a functional diagram of the generic bit latch and I/O buffer in each of the four ports. The bit latch, (one bit in the port SFR) is represented as a D type flip–flop. A ‘write to latch’ signal from the CPU latches a bit from the internal bus and a ‘read latch’ signal from the CPU places the Q output of the flip–flop on the internal bus. A ‘read pin’ signal from the CPU places the actual pin logical level on the internal bus. Some instructions that read a port read the actual pin, and other instructions read the latch (SFR). |
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