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TSC8051C2XXXA12IAB Datasheet(PDF) 9 Page - TEMIC Semiconductors |
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TSC8051C2XXXA12IAB Datasheet(HTML) 9 Page - TEMIC Semiconductors |
9 / 28 page TSC8051C2 Rev. A (10 Jan. 97) 9 Preview MATRA MHS Register Content SCON 00h SOCR 00h SP 07h TCON 00h TH0, TH1 00h TL0, TL1 00h TMOD 00h The internal RAM is not affected by reset. At power–on reset, the RAM content is indeterminate. Watchdog Reset RST Reset Circuitry Schmitt Trigger On–chip resistor RRST Power Fail Reset Figure 5. On–Chip Reset Configuration. An automatic reset can be obtained when VCC is turned on by connecting the RST pin to VCC through a 1 µF capacitor providing the VCC setting time does not exceed 1ms and the oscillator start–up time does not exceed 10ms. This power–on reset circuit is shown in Figure 6. When power comes on, the current drawn by RST starts to charge the capacitor. The voltage at RST is the difference between VCC and the capacitor voltage, and decreases from VCC as the capacitor charges. VRST must remain above the lower threshold of the Schmitt trigger long enough to effect a complete reset. The time required is the oscillator start–up time, plus 2 machine cycles. + VSS RST VRST RRST VCC TSC8051C2 VCC 1 mF Figure 6. Power–on Reset Circuit 6.6. Oscillator Characteristics XTAL1 and XTAL2 are respectively the input and output of an inverting amplifier which is configured for use as an on–chip oscillator. As shown in Figure 7. , either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected as shown in Figure 8. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide–by–two flip–flop. The minimum high and low times specified on the data sheet must be observed however. XTAL2 XTAL1 VSS Figure 7. Crystal Oscillator XTAL2 XTAL1 VSS NC EXTERNAL OSCILLATOR SIGNAL Figure 8. External Drive Configuration 6.7. Memory organization The memory organisation of the TSC8051C2 is the same as in the 80C51, with the exception that the TSC8051C2 has 4k bytes ROM, 256 bytes RAM, and additional SFRs. Details of the differences are given in the following paragraphs. In the TSC8051C2, the lowest 4k of the 64k program memory address space is filled by internal ROM. Depending on the package used, external access is available or not. By tying the EA pin high, the processor fetches instructions from internal program ROM. Bus expansion for accessing program memory from 4k upward is automatic since external instruction fetches occur automatically when the program counter exceeds 1FFFh. If the EA pin is tied low, all program memory fetches are from external memory. The execution speed is the same regardless of whether fetches are from external or internal program memory. If all storage is on–chip, then byte location 0FFFh should be left vacant to prevent an undesired pre–fetch from external program memory address 1000h. |
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