HY57V28820HC(L)T-I

Rev. 0.1/Jan. 01

2

PIN CONFIGURATION

DQ7

NC

DQ6

NC

DQ5

NC

DQ4

NC

NC

DQM

CLK

CKE

NC

A11

A9

A8

A7

A6

A5

A4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

DQ0

NC

DQ1

NC

DQ2

NC

DQ3

NC

NC

/WE

/CAS

/RAS

/CS

BA0

BA1

A10/AP

A0

A1

A2

A3

54pin TSOP II

400mil x 875mil

0.8mm pin pitch

PIN DESCRIPTION

PIN

PIN NAME

DESCRIPTION

CLK

Clock

The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK

CKE

Clock Enable

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

CS

Chip Select

Enables or disables all inputs except CLK, CKE and DQM

BA0, BA1

Bank Address

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

A0 ~ A11

Address

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9

Auto-precharge flag : A10

RAS, CAS, WE

Row Address Strobe, Col-

umn Address Strobe, Write

Enable

RAS, CAS and WE define the operation

Refer function truth table for details

DQM

Data Input/Output Mask

Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ7

Data Input/Output

Multiplexed data input / output pin

Power Supply/Ground

Power supply for internal circuits and input buffers

Data Output Power/Ground

Power supply for output buffers

NC

No Connection

No connection