HY57V28820HCLT-I datasheet(8/11 Pages) HYNIX

Part #	HY57V28820HCLT-I

Description	4Banks x 4M x 8bits Synchronous DRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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HY57V28820HC(L)T-I

Rev. 0.1/Jan. 01

8

AC CHARACTERISTICS II

Note :

1. A new command can be given tRRC after self refresh exit.

Parameter

Symbol

-6I

-KI

-HI

-8I

-PI

-SI

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

RAS Cycle Time

Operation

tRC

60

-

60

-

65

-

68

-

70

-

70

-

ns

Auto Refresh

tRRC

60

-

65

-

65

-

68

-

70

-

70

-

ns

RAS to CAS Delay

tRCD

18

-

15

-

20

-

20

-

20

-

20

-

ns

RAS Active Time

tRAS

42

100K

45

100K

45

100K

48

100K

50

100K

50

100K

ns

RAS Precharge Time

tRP

18

-

15

-

20

-

20

-

20

-

20

-

ns

RAS to RAS Bank Active Delay

tRRD

12

-

15

-

15

-

16

-

20

-

20

-

ns

CAS to CAS Delay

tCCD

1-

1-1

-

1-

1-1-

CLK

Write Command to Data-In Delay

tWTL

0

-

0

-

0

-

0

-

0

-

0

-

CLK

Data-In to Precharge Command

tDPL

2

-

2

-

2

-

2

-

2

-

2

-

CLK

Data-In to Active Command

tDAL

5

-

4

-

5

-

5

-

4

-

4

-

CLK

DQM to Data-Out Hi-Z

tDQZ

2

-

2

-

2

-

2

-

2

-

2

-

CLK

DQM to Data-In Mask

tDQM

0-

0-0

-

0-

0-0-

CLK

MRS to New Command

tMRD

2-

2-2

-

2-

2-2-

CLK

Precharge to Data

Output Hi-Z

CAS Latency = 3

tPROZ3

3

-

3

-3

-3-

3

-3-

CLK

CAS Latency = 2

tPROZ2

2

-

2

-2

-2-

2

-2-

CLK

Power Down Exit Time

tPDE

1

-

1

-

1

-

1

-

1

-

1

-

CLK

Self Refresh Exit Time

tSRE

1-

1-1

-

1-

1-1-

CLK

1

Refresh Time

tREF

-64-64

-64-

64

-64

-

64

ms

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