IC41C16100S

IC41LV16100S

Integrated Circuit Solution Inc.

7

DR010-0D 11/26/2004

(Recommended Operating Conditions unless otherwise noted.)

Symbol Parameter

Test Condition

Speed Min.

Max.

Unit

Input Leakage Current

Any input 0V

–5

5

µA

Other inputs not under test = 0V

Output Leakage Current

Output is disabled (Hi-Z)

–5

5

µA

0V

Output High Voltage Level

2.4

—

V

Output Low Voltage Level

—

0.4

V

Standby Current: TTL

RAS, LCAS, UCAS

—

2

mA

3.3V

—

1

Extended

5V

—

3

mA

3.3V

—

2

Standby Current: CMOS

RAS, LCAS, UCAS

5V

—

1

mA

3.3V

—

0.5

Operating Current:

RAS, LCAS, UCAS,

-45

—

190

mA

-50

—

160

Average Power Supply Current

-60

—

145

Operating Current:

-45

—

100

mA

-50

—

90

Average Power Supply Current

-60

—

80

Refresh Current:

RAS Cycling, LCAS, UCAS

-45

—

180

mA

-50

—

160

Average Power Supply Current

-60

—

145

Refresh Current:

RAS, LCAS, UCAS Cycling

-45

—

180

mA

-50

—

160

Average Power Supply Current

-60

—

145

Self Refresh Current

Self Refresh mode

—

—

300

µA

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.