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DS42MB200 Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DS42MB200 Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 14 page Pin Descriptions (Continued) Pin Name Pin Number I/O Description POWER V CC 2, 8, 14, 20, 29, 35, 38, 44 PV CC = 3.3V ± 5%. Each V CC pin should be connected to the VCC plane through a low inductance path, typically with a via located as close as possible to the landing pad of the V CC pin. It is recommended to have a 0.01 µF or 0.1 µF, X7R, size-0402 bypass capacitor from each V CC pin to ground plane. GND 5, 11, 17, 32, 41 P Ground reference. Each ground pin should be connected to the ground plane through a low inductance path, typically with a via located as close as possible to the landing pad of the GND pin. GND DAP P Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the LLP-48 package. It should be connected to the GND plane with at least 4 via to lower the ground impedance and improve the thermal performance of the package. Note: I = Input, O = Output, P = Power Functional Description The DS42MB200 is a signal conditioning 2:1 multiplexer and a 1:2 buffer designed to support port redundancy up to 4.25 Gb/s. Each input stage has a fixed equalizer that provides equalization to compensate about 5 dB of transmission loss from a short backplane trace (about 10 inches backplane). The output driver has pre-emphasis (driver-side equaliza- tion) to compensate the transmission loss of the backplane that it is driving. The driver conditions the output signal such that the lower frequency and higher frequency pulses reach approximately the same amplitude at the end of the back- plane, and minimize the deterministic jitter caused by the amplitude disparity. The DS42MB200 provides 4 steps of user-selectable pre-emphasis ranging from 0, -3, -6 and –9 dB to handle different lengths of backplane. Figure 1 shows a driver pre-emphasis waveform. The pre-emphasis duration is 200ps nominal, corresponds to 0.75 bit-width at 4 Gb/s. The pre-emphasis levels of switch-side and line-side can be individually programmed. The high speed inputs are self-biased to about 1.5V and are designed for AC coupling. The inputs are compatible to most AC coupling differential signals such as LVDS, LVPECL and CML. TABLE 1. LOGIC TABLE FOR MULTIPLEX CONTROLS MUX_S0 Mux Function 0 MUX_0 select switch_B input, SIB_0±. 1 (default) MUX_0 select switch_A input, SIA_0±. MUX_S1 Mux Function 0 MUX_1 select switch_B input, SIB_1±. 1 (default) MUX_1 select switch_A input, SIA_0±. TABLE 2. LOGIC TABLE FOR LOOPBACK Controls LB0A Loopback Function 0 Enable loopback from SIA_0± to SOA_0±. 1 (default) Normal mode. Loopback disabled. LB0B Loopback Function 0 Enable loopback from SIB_0± to SOB_0±. 1 (default) Normal mode. Loopback disabled. LB1A Loopback Function 0 Enable loopback from SIA_1± to SOA_1±. 1 (default) Normal mode. Loopback disabled. LB1B Loopback Function 0 Enable loopback from SIB_1± to SOB_1±. 1 (default) Normal mode. Loopback disabled. www.national.com 5 |
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