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XRT72L50 Datasheet(PDF) 3 Page - Exar Corporation |
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XRT72L50 Datasheet(HTML) 3 Page - Exar Corporation |
3 / 471 page áç áç áç áç XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. 1.2.1 I TABLE OF CONTENTS GENERAL DESCRIPTION ............................................................................................... 1 FEATURES ................................................................................................................................................. 1 APPLICATIONS ........................................................................................................................................... 1 Figure 1. Block Diagram of the XRT72L50 ..................................................................................................................... 1 Figure 2. Pin Out of the XRT72L50 ................................................................................................................................. 2 ORDERING INFORMATION ............................................................................................ 2 TABLE OF CONTENTS ................................................................................................................................. I PIN DESCRIPTIONS ........................................................................................................ 3 ELECTRICAL CHARACTERISTICS .............................................................................. 20 ABSOLUTE MAXIMUMS ............................................................................................................................. 20 DC ELECTRICAL CHARACTERISTICS ......................................................................................................... 20 AC ELECTRICAL CHARACTERISTICS ......................................................................................................... 20 AC ELECTRICAL CHARACTERISTICS (CONT.) ............................................................................................ 22 1.0 Timing Diagrams ................................................................................................................................. 26 Figure 3. Timing Diagram for Transmit Payload Input Interface, when the XRT72L50 Device is operating in both the DS3 and Loop-Timing Modes ....................................................................................................................................... 26 Figure 4. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L50 Device is operating in both the DS3 and Local-Timing Modes ............................................................................................................................... 26 Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L50 Device is operating in both the DS3/Nibble and Looped-Timing Modes ......................................................................................................... 27 Figure 6. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L50 Device is operating in the DS3/ Nibble and Local-Timing Modes .................................................................................................................... 27 Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) .................................... 28 Figure 8. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) .................................... 28 Figure 9. Transmit LIU Interface Timing - TxPOS and TxNEG are updated on the rising edge of TxLineClk .............. 29 Figure 10. Transmit LIU Interface Timing - TxPOS and TxNEG are updated on the falling edge of TxLineClk ............ 29 Figure 11. Receive LIU Interface timing - RxPOS and RxNEG are sampled on rising edge of RxLineClk .................. 30 Figure 12. Receive LIU Interface timing - RxPOS and RxNEG are sampled on falling edge of RxLineClk .................. 30 Figure 13. Receive Payload Data Output Interface Timing ........................................................................................... 31 Figure 14. Receive Payload Data Output Interface Timing (Nibble Mode Operation) ................................................... 31 Figure 15. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ......................................... 32 Figure 16. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) ................................... 32 Figure 17. Microprocessor Interface Timing - Intel-type Programmed I/O Read Operation .......................................... 33 Figure 18. Microprocessor Interface Timing - Intel-type Programmed I/O Write Operation .......................................... 33 Figure 19. Microprocessor Interface Timing - Motorola-type Programmed I/O Read Operation .................................. 34 Figure 20. Microprocessor Interface Timing - Motorola-type Programmed I/O Write Operation .................................. 34 Figure 21. Microprocessor Interface Timing - Reset Pulse Width ................................................................................. 34 2.0 The Microprocessor Interface Block ................................................................................................. 35 2.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNASL ............................................................................................ 35 Figure 22. Block Diagram of the Microprocessor Interface Block ................................................................................. 35 TABLE 1: DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE INTEL AND MOTOROLA MODES ......................................................................................................................................... 36 TABLE 2: DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS - OPERATING IN THE INTEL MODE ............................... 36 2.2 INTERFACING THE XRT72L50 DS3/E3 FRAMER TO THE LOCAL µC/µP VIA THE MICROPROCESSOR INTERFACE BLOCK 37 2.2.1 Interfacing the XRT72L50 DS3/E3 Framer to the Microprocessor over an 8 bit wide bi-directional Data Bus 37 TABLE 3: DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS - OPERATING IN THE MOTOROLA MODE ................ 37 2.2.2 Data Access Modes ................................................................................................................................ 38 2.2.2.1 Data Access using Programmed I/O ............................................................................................. 38 Figure 23. Microprocessor Interface Timing - Intel-type Programmed I/O Read Operation .......................................... 39 Figure 24. Microprocessor Interface Timing - Intel-type Programmed I/O Write Operation .......................................... 40 Figure 25. Microprocessor Interface Timing - Motorola-type Programmed I/O Read Operation .................................. 41 2.3 ON-CHIP REGISTER ORGANIZATION ..................................................................................................................... 42 2.3.1 Framer Register Addressing ................................................................................................................... 42 Figure 26. Microprocessor Interface Timing - Motorola-type Programmed I/O Write Operation .................................. 42 TABLE 4: REGISTER ADDRESSING OF THE FRAMER PROGRAMMER REGISTERS .................................................................. 42 2.3.2 Framer Register Description ................................................................................................................... 46 |
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