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16
Preliminary
8-16
Military 5.0V pASIC 1 Family
High Drive Buffer
[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25
°C.
Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.
Clock Drivers
Propagation Delays (ns) [4]
Symbol
Parameter
Wired Together
Fanout
12
24
48
72
96
14.0
4.9
tIN
High Drive Input Delay
2
3.5
5.0
3
4.0
4.8
5.6
44.1
4.8
14.2
5.1
tINI
High Drive Input,
2
3.7
5.2
Inverting Delay
3
4.2
5.0
5.8
44.3
5.0