GENNUM CORPORATION

20582 - 3

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DETAILED DESCRIPTION

DETAILED DESCRIPTION

DETAILED DESCRIPTION

DETAILED DESCRIPTION

The GS9035C receives either a single-ended or differential

PECL serial data stream at the DDI and DDI inputs. It locks

an internal clock to the incoming data and outputs the

differential PECL retimed data signal and recovered clock

on outputs SDO/SDO and SCO/SCO respectively. The

timing between the input, output, and clock signals is

shown below.

Fig. 8 Input/Output Clock Signal Timing

The GS9035C reclocker contains four main functional

blocks: the Phase Locked Loop, Auto/Manual Data Rate

Select, Frequency Acquisition, and Logic Circuit.

1. PHASE LOCKED LOOP (PLL)

The Phase Locked Loop locks the internal PLL clock to the

incoming data rate. A simplified block diagram of the PLL is

shown below. The main components are the VCO, the

phase detector, the charge pump, and the loop filter.

Fig. 9 Simplified Diagram of the PLL

1.1 VCO

The VCO is a differential low phase noise, factory trimmed

design that provides increased immunity to PCB noise and

precise control of the VCO center frequency. The VCO

operates between 143 and 360Mb/s and has a pull range of

-13 +25% about the center frequency depending on the

signal data rate. A single low impedance external resistor,

the PLL's sensitivity to PCB noise.

frequencies. When SMPTE = SS0 = logic 1, the VCO center

SMPTE/SS0 combinations, the VCO center frequency

applications is 365

Ω.

The VCO and an internal divider generate the PLL clock.

Divider moduli of 1, 2, and 4 allow the PLL to lock to data

rates from 143Mb/s to 360Mb/s. The divider modulus is set

by

the

AUTO/MAN,

SMPTE,

and

SS[1:0]

pin

(see Auto/Manual Data Rate Select section for further

details).

When the input data stream is removed for an excessive

period of time (see AC electrical characteristics table), the

VCO frequency can drift from the previously locked

frequency up to the maximum shown in Table 1.

DDI

SDO

SCO

50%

DDI/DDI

LF+

LFS

LF-

VCO

DIVISION

2

PHASE

DETECTOR

INTERNAL

PLL CLOCK

CHARGE

PUMP

LOOP

FILTER

TABLE 1: Frequency Drift Range (when PLL loses lock)

LOSES LOCK FROM

MIN (%)

MAX(%)

143Mb/s lock

-21

21

177Mb/s lock

-12

26

270Mb/s lock

-13

28

360 Mb/s lock

-13

24

0

100

200

300

400

500

600

700

800

0

200

400

600

800

1000

1200

1400

1600

1800

ƒH

ƒL

SMPTE=1

SSO=1