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PL3843B Datasheet(PDF) 5 Page - Cystech Electonics Corp. |
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PL3843B Datasheet(HTML) 5 Page - Cystech Electonics Corp. |
5 / 15 page CYStech Electronics Corp. Spec. No. : C510P8 Issued Date : 2003.04.24 Revised Date : Page No. : 5/15 PL384XBP8 CYStek Product Specification Figure 1: Open Loop Test Circuit 8 7 6 5 4 3 2 1 VREF 0.1uF VI OUTPUT GROUND 0.1uF 1W 1k VI VREF OUTPUT A RT 2N2222 4.7k 1k 4.7k 100k 5k COMP VFB ISENSE RT/CT CT GROUND ISENSE ADJUST ERROR AMP. ADJUST High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5kΩ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Figure 2:Timing Resistor vs Oscillator Frequency 1 10 100 10 100 1000 Oscillator Frequency---fosc(kHz) CT=100pF 200pF 500pF 10nF 5nF 2nF 1nF Vi=15V,TA=25 ℃ Figure 3:Output Dead-Time vs Oscillator Frequency 1 10 100 10 100 1000 Oscillator Frequency---fosc(kHz) CT=200pF CT=500p F CT=1nF CT=2nF CT=10nF CT=5nF CT=100pF Vi=15V TA=25 |
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