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PAC560GT Datasheet(PDF) 3 Page - California Micro Devices Corp |
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PAC560GT Datasheet(HTML) 3 Page - California Micro Devices Corp |
3 / 3 page ©2000 California Micro Devices Corp. All rights reserved. 2/00 3 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com CALIFORNIA MICRO DEVICES PACGTL RECOMMENDED LAYOUT FOR SOCKET 370 (OPTION B) FOR CELERON AND MENDOCINO CPUs Note: This option requires 2 metal layers in board routing for all 119 GTL termination lines. Please note that the second layer only uses 6 short traces, minimizing potencial interference with other traces, and also minimizing the number of vias. |
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