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MAX1157BCUI Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX1157BCUI Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 15 page Track and Hold (T/H) In track mode, the internal hold capacitor acquires the analog signal (see Figure 4). In hold mode, the T/H switches open and the capacitive DAC samples the analog input. During the acquisition, the analog input (AIN) charges capacitor CHOLD. The acquisition ends on the second falling edge of CS. At this instant, the T/H switches open. The retained charge on CHOLD rep- resents a sample of the input. In hold mode, the capac- itive DAC adjusts during the remainder of the conversion time to restore node T/H OUT to zero within the limits of 14-bit resolution. Force CS low to put valid data on the bus after conversion is complete. Power-Down Modes Select standby mode or shutdown mode with R/C during the second falling edge of CS (see Selecting Standby or Shutdown Mode section). The MAX1157/MAX1159/ MAX1175 automatically enter either standby mode (refer- ence and buffer on), or shutdown (reference and buffer off) after each conversion depending on the status of R/C during the second falling edge of CS. Internal Clock The MAX1157/MAX1159/MAX1175 generate an internal conversion clock to free the microprocessor from the bur- den of running the SAR conversion clock. Total conver- sion time after entering hold mode (second falling edge of CS) to end-of-conversion (EOC) falling is 4.7µs (max). Applications Information Starting a Conversion CS and R/C control acquisition and conversion in the MAX1157/MAX1159/MAX1175 (see Figure 2). The first falling edge of CS powers up the device and puts it in acquire mode if R/C is low. The convert start CS is ignored if R/C is high. The MAX1157/MAX1159/ MAX1175 need at least 6ms (CREFADJ = 0.1µF, CREF = 10µF) for the internal reference to wake up and settle before starting the conversion if powering up from shut- down. Reset the MAX1157/MAX1159/MAX1175 by tog- gling RESET with CS high. The next falling edge of CS begins acquisition. Selecting Standby or Shutdown Mode The MAX1157/MAX1159/MAX1175 have a selectable standby or low-power shutdown mode. In standby mode, the ADC’s internal reference and reference buffer do not power down between conversions, elimi- nating the need to wait for the reference to power up before performing the next conversion. Shutdown mode 14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range 8 _______________________________________________________________________________________ Figure 2. MAX1157/MAX1159/MAX1175 Timing Diagram tCSL tCSH tACQ tDH R/C CS EOC D0–D13 tDS tDV tEOC tDO tBR tCONV HIGH-Z REF POWER- DOWN CONTROL HIGH-Z DATA VALID Figure 3. Typical Application Circuit for the MAX1157/MAX1159/ MAX1175 MAX1157 MAX1159 MAX1175 ANALOG INPUT AIN AVDD +5V ANALOG +5V DIGITAL DVDD D0–D13 14-BIT WIDE µP DATA BUS 10 µF 0.1 µF 0.1 µF 0.1 µF R/C CS AGND DGND REFADJ REF EOC RESET |
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