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LCK4973 Datasheet(PDF) 8 Page - Agere Systems |
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LCK4973 Datasheet(HTML) 8 Page - Agere Systems |
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8 / 16 page  88 Agere Systems Inc. Data Sheet February 2003 Low-Voltage PLL Clock Driver LCK4973 Functional Description (continued) Device Programming (continued) 2336.a (F) Figure 5. 20 MHz Source Example The Lnv_Clk input pin, when asserted, will invert the Qc2 and Qc3 outputs.This inversion does not affect the output-output skew of the device and allows for the development of 180° phase-shifted clocks. This output can also be used as a feedback output or routed to a second PLL to generate early/late clocks. Figure 5 on page 8 shows a 180° phase-shift configuration. Zero-Delay Buffer Use The LCK4973 can be used as a zero-delay buffer due to the external feedback of the device. Using one of the inputs as a feedback to the PLL eliminates the propagation delay through the device. A near-zero delay is produced by the PLL aligning to the output edge to the input reference edge. The static phase offset and the relative delay between the inputs and outputs are affected by the reference frequency. This is because the static phase offset is a function of the reference clock and Tpd of the LCK4973 is a function of the configuration used. It is most likely that the LCK4973 will be used as a zero-delay buffer in a nested clock-tree application. In these instances, the LCK4973 offers a LVPECL clock input as the PLL reference. This allows the user to utilize the exceptional skew performance of the device as the primary clock distribution device. The device can then lock onto the LVPECL reference and translate, with near-zero delay, to low-skew LVCMOS outputs. These clock trees will show tighter skews than CMOS fanout buffer clock trees. SYNC Output When the output frequencies are not integer multiples of each other, there is a need for a signal for synchronization purposes. The SYNC output is designed to address this need. The Qa and Qc banks of outputs are monitored by the device, and a low- going pulse (one period in duration, on period before the coincident rising edges of Qa and Qc) is provided. The duration and placement of the pulse is dependent on the highest of Qa and Qc output frequencies. The timing diagram, (Figure 8 on page 10) show the various waveforms for SYNC. Note: SYNC is defined for all possible combinations of Qa and Qc, even though the lower frequency clock should be used as a synchronizing signal in most cases. fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2 1 1 0 1 1 1 1 1 1 LCK4973 Qa Qb Qc QFB 33 MHz (PCI) 50 MHz (PROCESSOR) 50 MHz (PROCESSOR) 20 MHz (ETHERNET) 4 4 4 20 MHz Input Ref Ext_FB |
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